This 4 hours tutorial will present following topics:
TCAD overview and state of TCAD TCAD modeling and application topics for reliability

• ESD
• hot carrier effects
• reliabilty/trap models
• radiation effects: single even upsets, total dose effects

The presentation will be followed by a TCAD tool demo and Q/A

Speakers:		Dean Lewisa and Philippe Perdub
		a IXL ENSEIRB CNRS UMR 5818 , Université Bordeaux, Talence France b CNES- French Space Agency, Toulouse France

Laser techniques are getting more and more a key for Integrated Circuits (IC) analysis. They allows front side and backside failure analysis and can be used for debug purpose and design optimization. These contactless techniques are non destructive and give sub-micronic resolution. In addition sub-nanosecond timing analysis can be achieved. Today, some of these techniques are well know and widely used in industrial environment. Thermal laser Stimulation is an unique method to localize IC physical defect that induced abnormal current consumption. Other techniques based on photoelectric effect such as OBIC have already proven their usefulness and have opened a wide range of application in both static and dynamic mode. Dynamic laser stimulation techniques are widely used by top IC manufacturers. Additionally to laser stimulation (pump techniques), probe techniques, Laser Voltage Probing for instance, extend the field of laser IC testing applications. Moreover, progresses in laser and metrology allows performing new probe techniques from laboratory to industry. Others laser techniques are going to trigger remarkable applications.
The main purpose of this tutorial is to describe these techniques from there principles to there applications. Although we focus on existing techniques, we also present some emerging applications of laser for IC testing.

Tutorial 3: Applications of Scanning Probe Microscopy for Failure Analysis

Speaker:		Peter De Wolf (dewolf@veeco.fr)
		VEECO INSTRUMENTS SAS, Dourdan France

Since its invention, the standard capability of the Atomic Force Microscope of nanometer-scale topography imaging has been augmented with a wide range of imaging and characterization modes. Many of these modes can be applied for the failure analysis of semiconductor devices with unrivaled spatial resolution. This tutorial gives an overview of the different scanning probe microscopy modes that can be used for this purpose, including electrical, magnetic, thermal as well as optical methods.

Electric Field (EFM) and Magnetic Field Microscopy (MFM). In EFM and MFM, the distribution of the electric and/or magnetic fields can be measured and correlated to the surface topography. These techniques allow one to map variations in charges, surface potentials, electric fields, magnetic fields with high spatial resolution (~ 20nm). These techniques have proven useful to localize defects on devices under operation.

Scanning Thermal Microscopy (SThM). When the AFM tip is equipped with a tiny temperature sensor (for example as thermistor or thermocouple), high-resolution temperature mapping can be performed. Spatial resolution, temperature sensitivity and other specifications will be illustrated by a number of failure anlysis case studies.

Tunneling AFM (TUNA) and Conductive AFM (C-AFM). Tunneling AFM makes it possible to measure local tunneling currents (40 fA - 100 pA) through thin dielectric films with nanometer-scale spatial resolution. Applications include imaging of thickness variations in dielectric films with a thickness in the range of a few Angstom to 50 nm, and localization of electrically weak spots or local degradation. The TUNA method yields local currents down to the fA range with a lateral resolution of 10 nm. Application examples include the detection of gate oxide edge thinning, localization of defects in silicon oxide and high-k dielectrics, as well as general conductivity uniformity measurements.

Scanning Capacitance Microscopy (SCM) and Scanning Spreading Resistance Microscopy (SSRM). SCM and SSRM allow one to image the two-dimensional carrier distribution on cross-sectioned or planar devices with nanometer spatial resolution. In SCM, the probe and sample form a small MOS capacitor whose capacitance is a measure for the local carrier concentration or charge properties. In SSRM a bias voltage is applied between probe and sample, resulting in a current which is proportional to the local carrier concentration. Both methods will be discussed in terms of instrumentation and operation. 2-D resistance maps obtained on various materials and devices (sub-micron MOSFETs, III-V devices, bipolar transistors,...) will be shown and discussed. Failure analysis case studies will be used to illustrate the capabilities and limitations of these techniques for two-dimensional carrier profiling. It will also been demonstrated how these techniques can be used on operating (active) devices.

High-resolution Probing using multiple SPM probes. When replacing conventional probers, with SPM-based probers, a big enhancement is obtained in positioning accuracy and probe contact size. It will be discussed how multiple SPM-based probers allow to perform electrical probing experiments on small structures. Limitations and capabilities will be illustrated by some case studies.

Nanoscopic Four-Point-Probe (NFPP). In the nanoscopic four-point probe measurements a miniaturized 4-point-probe (probe spacing only a few īm) is used to do local sheet resistance and resistivity measurements. The smaller geometry allows one to use lower forces and more precise positioning as compared to conventional FPP probing. The lower forces allow to have a lower (or no) penetration into the sample and also to work on various softer materials.

Scanning Near-field Optical Microscopy (SNOM). In SNOM, the SPM tip is a fiber with small aperture (< 100nm). The aperture is scanned in close proximity to the sample and used to illuminate or collect light in the near-field. Several setups are possible including reflection & transmission mode, illumination & collection mode, etc. An overview will be given of the existing modes and example swill be used to illustrate how these modes can be applied for failure anlysis.

Tutorial 4: Virtual Reliability Qualification

Speaker:		G.Q. Zhang
		Technical University of Eindhoven and Philips Centre For Industrial Technology, Eindhoven, The Netherlands

The rapid technological development trends of microelectronics and Microsystems are mainly characterized by miniaturization down to nano-scale, increasing levels of technology and function integration and eco-design, while the business trends are mainly characterized by cost reduction, short-time-to-market and outsourcing. These trends lead to increased chances and consequences of failures, increased design complexity, decreased product development and qualification times, dramatically decreased design margins and increased difficulties to meet quality, robustness and reliability requirements. To achieve competitive product/process development and manufacturing excellence, it is vital and a must to know and to apply the state-of-the-art methods for virtual reliability qualification.

Content & scope:

1. Development trends of Microelectronics and Microsystems
2. Status quo of reliability qualification and assessment
3. The state-of-the-art of virtual reliability qualification (i.e., designing for reliability), including the basic theories and methodologies
4. Case study of virtual reliability qualification covering typical failure modes related with wafer backend, IC packaging and board level assembly, such as (not limited to)
   • Various cracks
   • Delamination
   • Wire bonding failures
   • Solder fatigues
   • Moisture induced failures
   • Warpage, etc.
5. Challenges and future perspectives

Tutorial 5: ESD Testing: HBM to very fast TLP

Speaker:		Horst A. Gieser
		Fraunhofer Institut für Zuverlässigkeit und Mikrointegration - IZM, München

ESD testing must not be limited to the controlled simulation of electrostatic discharge events in an ESD tester according to the stress models Human Body Model, Machine Model and Charged Device Model, which for the purpose of qualification yield only a failure threshold typically in Volts. In addition, Transmission Line Pulse (TLP) systems providing information on both voltage and current are key tools for successful development of ESD protection, especially in an era of increased demand for robustness, in conflict with shrinking feature sizes. The sys-tems differ in their configuration, pulse duration, source impedance and method of pulse metrology. Most of them employ 100ns wide square pulses addressing the domain of the Human Body Model. "Very Fast" TLP systems with pulse lengths as short as few ns address Charged Device Model time scale events of protection devices and structures to be protected. This tutorial provides background information and useful hints for qualification tests with respect to current standards. It further explains 100ns and vfTLP systems in their specific application.