Full ball shear metrology as defect detection and analysis tool for solder joint reliability assessment on direct immersion gold technology

C.K. Chen, W.A. Tan, H.S. Goh, Y.S. Yip, W.T. Saw
Intel Technology Malaysia, Bayan Lepas FIZ, Phase 3, Halaman Kampung Jawa, Penang, Malaysia.

Direct Immersion Gold (DIG) technology was developed as alternative surface finish for flip chip ball grid array substrate to address brittle solder joint issue resulted from Electroless Nickel Immersion Gold (ENIG) surface finish. This paper will discuss the defect detection metrology of Full Ball Shear as a breakthrough analysis for tiny voids in order to assess solder joint reliability of DIG substrates and its success of identifying potential solution path for tiny void issue.

Characterization and fatigue damage simulation in SAC solder joints

M.Erinc, P.J.G.Schreurs, G.Q.Zhang, M.G.D.Geers
Materials Technology, Department of Mechanical Engineering, Eindhoven University of Technology Eindhoven 5600 MB, The Netherlands

Lead-free solder balls with a composition 95.5Sn-4.0Ag-0.5Cu (SAC) are examined both microstructurally and mechanically. The initial microstructure is investigated by electron microscopy using solder balls reflowed on Cu/Ni/Au metallization. Specially prepared single joint specimens with one solder ball, and flat samples of copper plates connected by SAC solder paste are loaded under monotonous shear and tension. Damaged samples are examined by electron microscopy, where a strong effect of microstructure on the crack path is observed. Deformation is observed to localize at the metallization/solder interface and also at the tin colony boundaries. Nano-indentation is used to get material data for different microstructural entities within the solder ball, with an emphasis on intermetallic compounds. Raw data from the indentation experiments are then used to predict yield strength and hardening parameters through an inverse approach, i.e. using a finite element simulation of the indentation process. Fatigue damage initiation and propagation in a solder bump are simulated by using interfacial debonding models. Damage is assumed to occur at interfaces modeled through cohesive zones in the material, placed at the internal boundaries where damage is found to localize experimentally. The degradation throughout the cycling process is accounted by an interfacial damage evolution law.

Effect of long and short Pb-free soldering profiles of IPC/JEDEC J-STD-020 on plastic SMD packages

P. Alpern^a, K.C. Lee^b and R. Tilgner^a
a Infineon Technologies AG, Corporate Assembly and Testing, Munich, Germany
^b Infineon Technologies Asia Pacific Pte Ltd, Product Reliability and Analysis, Singapore 349253

The Pb-free soldering temperature-time profile T(t) in the IPC/JEDEC J-STD-020 specification, which is used in the moisture sensitivity level (MSL) classification of plastic SMD packages, has a wide time range. We found that in a thick package, MQFP-80 the long soldering profile is worse than the short one whereas in a thin package, TSSOP-38 the result is surprisingly the reverse. Because moisture diffusion inside the package is much slower than thermal diffusion, the wide time range in T(t) profile is found to have an effect on the MSL of packages with different geometries. The results suggest a strong need to reduce the width of soldering range in the J-STD-020 specification. Further studies done on A2-coated leadframe packages, namely DSO-20 and MQFP-80, found quite similar MSL performance for both long and short soldering profiles.

Reliability of Low-Cost PCB Interconnections for Telecommunication Applications

G. Duchamp, F. Verdier, Y. Deshayes, F. Marc, Y. Ousten, Y. Danto
Laboratoire IXL - ENSEIRB - UMR CNRS 5818, 33405 Talence, France

Today the low cost PCB interconnections are widely used for domestic telecommunication applications. These technologies are limited by the possible variation of the performances of substrates and metallization during operating life. The knowledge of the behaviour of these parameters under stress conditions allows to optimise the design safety margins and to predict a probable lifetime. In this paper we show that the proposed structures (rings and stub resonators) could be used to discriminate the degradation sources.

Effect of bonding pressure on reliability of flip chip joints on flexible and rigid substrates

L. Frisk, A. Seppälä and E. Ristolainen
Institute of Electronics, Tampere University of Technology P.O.Box 692, 33101 Tampere, Finland

In this study the effect of bonding pressure on the reliability of adhesive flip chip joints was evaluated. Two different substrates were used: rigid FR-4 board and flexible liquid crystal polymer (LCP) board. The reliability of the test samples was studied in a temperature cycling test, carried out between temperatures of -40 °C and 125 °C. To determine the exact time of a failure the resistance of each test sample was measured using continuous real-time measurement. A clear difference between different substrates was observed in the test. Cross sections of the samples were made in order to analyse the failure mechanisms.

How to study delamination in plastic encapsulated devices

Hélène Frémont, Jean-Yves Delétage, Kirsten Weide-Zaage*, Yves Danto
IXL ENSEIRB CNRS UMR 5818 , Université Bordeaux 1 351 cours de la Libération, 33405 Talence Cedex France
*Laboratorium für Informationstechnologie, University of Hannover, Schneiderberg 32, 30167 Hannover GERMANY

Delaminations are a major concern in plastic encapsulated devices (PED). This paper presents three complementary methods to evaluate the sensitivity of PED to this problem. Analytical models are fast to implement, and permit to derive a comparative evaluation between different packages. To refine the results, finite element models, necessitating longer calculation times are very useful, but need to be validated by real measurements, which can be done with assembly test chips.

Characterization and Modelling of Moisture Driven Interface Failures

M.A.J. van Gils^a, P.J.J.H.A. Habets^b, G.Q. Zhang^a,b, W.D. van Driel^a, P.J.G. Schreurs^b
aPhilips, P.O. Box 218, 5600 MD, Eindhoven, The Netherlands
^bEindhoven University of Technology, P.O. Box 513, 5600 MB, Eindhoven, The Netherlands. g.q.zhang@philips.com

Since moisture sensitivity level (MSL) tests are part of the international reliability qualification standards, all the microelectronics components/products have to pass these specifications. Therefore, it is important to be able to efficiently and accurately characterize and predict the moisture related material and interface behaviour in the real manufacturing, processing, testing and application conditions. This paper focuses on our research efforts in and results of developing and verifying efficient and accurate characterization and modelling methods for moisture driven interface failures. The methodology incorporates the characterization of the strength of critical interfaces as function of temperature and humidity using the four-point bending test. Using multi-physics-based Finite Element (FE) models, which take into account both the moisture and thermo-mechanical related failure mechanisms, enables the prediction of interface failures. The developed methodology is used for understanding the observed interface failures of an industry carrier.

Metal migration in epoxy encapsulated ECL devices

C. Zhang, P. Yalamanchili, M. Al-Sheikhley and A. Christou
Materials Science and Engineering and Reliability Engineering Center University of Maryland, College Park, MD 20742

The present investigation identifies migrative resistive shorts as the primary mode of failure for ECL power devices from field failures. In the present investigation, a number of analytical tools have been applied in order to identify and characterize the failure mechanism. These techniques included environmental scanning acoustic microscopy (ESEM), energy dispersive x-ray spectroscopy (EDX), scanning acoustic microscopy (C-SEM). Devices which were analyzed were selected so as to compare control, and untested devices with field returns which had failed as a result of either shorts between bond pads or the presence of leakage paths between bond pads. The failed devices from field returns were in two categories: returns with no destructive analysis performed, and returns with destructive analysis. Hence we were able to reach conclusions on the effect of destructive analysis on disturbing the failure site. We also performed accelerated stress testing on devices from a single date lot so as to attain projected mean time to failure and hence develop a statistically valid reliability model.

Low frequency noise as a reliability diagnostic tool in compound semiconductor transistors
(INVITED)
N. Labat, N. Malbert, C. Maneux, A. Touboul
Laboratory IXL - CNRS - ENSEIRB- Université Bordeaux 1
351 Cours de la Libération, 33405 Talence Cedex, FRANCE

Low frequency (LF) noise can be used as a diagnostic technique to analyse the quality and reliability of electron devices. Different reviews of the fundamental and excess LF noise sources in compound semiconductor transistors have been published in previous papers [1,2,3]. Examples of experimental correlation between LF noise and parasitic effects (i.e. electrical performance degradation) or failure mechanisms will be described for various compound semiconductor devices.

Reliability Investigation of Gallium Nitride HEMT

A. Sozza^a,b,c, C. Dua^a, E. Morvan^a , B. Grimbert^d, V. Hoel^d , S.L. Delage^a N. Chaturvedi^d, R. Lossy^d, J. Wuerfl^d
aTRT/Tiger, Domaine de Corbeville, 91404 Orsay Cedex, France
^b DEI, Universit€ degli Studi di Padova, 35131,Padova, Italy
^c IXL, Universit‰ Bordeaux 1, 33405 Talence Cedex, France
^d IEMN/Tiger Avenue Poincar‰,59652 Villeneuve d'Ascq, France
^e FBH, Ferdinand-Braun-Institut fuer Hoechstfrequenztechnik, 12489 Berlin, Germany

III-N HEMT is one of the most promising transistor for the next generation of RF power devices. Despite the impressive results on power density obtained using discrete devices and total output power for GaN-based amplifier announced in 2003, reliability demonstration is the key issue before devices can be fielded in practical applications. In this article test procedures and samples are described and the last results concerning storage and DC life tests are presented. Schottky barrier degradation was observed as a key factor for the metallurgical tests. DC life-tests showed a slow and steady drain current drop followed by stabilization as a function of time.

Hot carrier aging degradation phenomena in GaN based MESFETs

F. Rampazzo^a, R. Pierobon^a, D. Pacetta^a, C. Gaquiere ^b, D.Theron ^b, B. Boudart^c, G. Meneghesso^a*, E. Zanoni^a
a University of Padova, Department of Information Engineering, and INFM - UdR Padova, Padova, Italy
^b Institut d'Eletronique et de Microelectronique du Nord, CNRS 8520, Départment Hyperfréquences et Semiconducteurs, Cité Scientifique, F-59652, Villeneuve d'Ascq Cedex, France
^c Laboratoire Universitaire de Science Appliquées de Chebourg, LUSAC, Site Universitaire, BP 78, F-50130 Cherbourg-Octeville, France

In this paper hot carrier degradation study in unpassivated and passivated GaN MESFETs will be presented: the observed drain current decrease will be proven to be consequent of a drain access resistance increase. In order to discriminate the effects due to traps on the device surface from those related with epitaxial material substrate and its interfaces, the influence of illumination on the drain current has been investigated by means of DC and gate-lag pulsed characterization. The measurements under light and under dark conditions lead us to suppose that the drain access resistance increase can be attributed to the generation of deep levels and/or to increased trapped charge after hot-carrier test on the device surface in the access regions between the gate and the drain contacts. The amount of degradation has been found to be remarkably higher in unpassivated devices with respect to passivated ones. Hot carrier degradation has been observed to be recovered by thermal or room temperature storage without applied bias.

Temperature-dependent breakdown and hot carrier stress of PHEMTs

P. Cova, N. Delmonte, G. Sozzi, R. Menozzi
Dipartimento di Ingegneria dell'Informazione, University of Parma
Parco Area delle Scienze, 181/A - 43100 Parma, Italy

The main issues this work addresses, with reference to commercial GaAs PHEMTs, are the temperature dependence of the off-state breakdown voltage (BV_DG), the physical mechanisms that determine it, and the relationship between BVDG and device degradation and failure, as determined by accelerated step-stress performed at temperatures ranging from 25 to 100°C. BV_DG is seen to decrease with temperature between room temperature and 160°C. Temperature-dependent analysis of the gate leakage current indicates that thermionic-field emission and thermionic emission over a field-dependent barrier are the limiting mechanisms for off-state breakdown. Room-temperature, hot carrier step-stress tests with 24 h step duration show reduced IDSS after the stress and a tight correlation between the BV_DG measured at I_G = - 1 mA/mm and the stress bias producing substantial device degradation or catastrophic failure. Shorter (2 h) step stress experiments carried out between 25 and 100°C again show a tight correlation between the BV_DG measured at IG = - 1 mA/mm and the stress bias producing dramatic degradation or failure. This correlation, coupled with the negligible temperature dependence of the breakdown voltage in this temperature range, results in temperature-independent device degradation.

On-wafer low frequency noise measurements of SiGe HBTs: Impact of technological improvements on 1/f noise

B. Grandchamp, C. Maneux, N. Labat, A. Touboul, T. Zimmer
Laboratory IXL - CNRS - ENSEIRB- Université Bordeaux 1
351 Cours de la Libération, 33405 Talence Cedex, FRANCE

This work deals with low frequency noise measurements on 0.13μm SiGe:C Heterojunction Bipolar Transistor (HBT) of a BiCMOS technology. The method achieved here, is the extraction of the pre-eminent low frequency noise source, assuming to be located in the base, from collector noise measurement. HBT RF test structures with several emitter areas have been measured at wafer level. The extraction of 1/f noise parameters from measurements leads to a technological free-scale figure-of-merit, K_B. The comparison of its value with previous generations data allows to draw some conclusions on the impact of HBT technological process variants on improvement of its low frequency noise. Indeed, SiGe HBT LF noise reflects either crystallographic quality of the epitaxial structure and influence of defects located at interfaces, mainly in the emitter-base periphery.

Reliability of power electronic devices against cosmic radiation-induced failure
(INVITED)
G. Soelkner^a, W. Kaindl^b, H.-J. Schulze^a, G. Wachutka^b
a Infineon Technologies, Automotive & Industrial, Balanstr. 59/2, 81730 Munich, German
^b Inst. for Physics of Electrotechnology, Munich Univ. of Technology, Arcisstr. 21, Munich, Germany

Cosmic radiation has been identified as a decisive factor for power device reliability. Energetic neutrons create ionizing recoils within the semiconductor substrate which may lead to device burnout. Originally, this failure mechanism was attributed to high voltage devices only. However, the results of accelerated nucleon radiation tests made it clear that cosmic radiation-induced breakdown can no longer be disregarded for the design of power devices of voltages classes as low as 500V. Extensive device simulations supported by ion irradiation experiments gave quantitative results and may in the future allow for a predictive assessment of the cosmic radiation hardness of a specific device design

The Role of the Parasitic BJT Parameters on the Reliability of New Generation Power MOSFET during Heavy Ion Exposure

F. Velardi^a, F. Iannuzzo^a, G. Busatto^a, A. Porzio^a, A. Sanseverino^b, G. Currò^c, A. Cascio^c, F. Frisina^c
aD.A.E.I.M.I., Università degli Studi di Cassino, Via Di Biasio, 43 - 03043 CASSINO (FR) - ITALY
^bD.I.E.T., Università degli Studi di Napoli,Via Claudio, 21 - 80125 NAPOLI - ITALY
^cST-Microelectronics - Stradale Primosole, 50 - 95100 CATANIA - ITALY

In this paper we propose an experimental study, supported by numerical simulation, of the role of the parasitic transistor on the charge generation phenomenon observed during the impact of heavy ions on medium voltage power MOSFET. The amount of the generated charge is reliant on the gain of the BJT which decreases with an increase of the epitaxial layer thickness in high injection levels and low fields. The charge amplification can induce a premature damage of the device under test and then radically reduces its reliability to sustaining single event effects.

Semiconductors in high temperature applications - a future trend in automotive industry

Michael Goroll^a, Reinhard Pufall^a, Werner Kanert^a, Boris Plikat^b
a Infineon Technologies AG, Automotive & Industrial Division, Balanstraße 73, D-81541 Munich, Germany
^b Infineon Technologies AG, Corporate Assembly & Test Division, Regensburg, Germany

Semiconductors for high temperature become increasingly important for automotive applications. Typical junction temperatures of 150°C (microcontrollers)/200°C (power devices) are requested. To fulfil failure rates of <1ppm in automotive applications a lot of investigations result in the following consequences: new design libraries, test concepts, technology and product qualification strategies. In the paper the effort for semiconductor supplier to be able to provide devices for high temperature applications will be presented. Investigations to assure safe high temperature device operation advanced by a European funding project will be introduced. A qualification concept proposal regarding AEC-Q100 will be discussed.

Analysis of PowerMOSFET chips failed in thermal instability

A. Castellazzi^a, H. Schwarzbauer^b, D. Schmitt-Landsiedel^c
a Institute of Physics of Electrotechnology, Munich University of Technology, Munich, Germany
^b Siemens Ag,CT PS2, Otto-Hahn-Ring 6, 81730 Munich, Germany c Institute of Technical Electronics, Munich University of Technology, Munich, Germany

Recent developments in power electronics foresee the extensive use of new-generation low-voltage PowerMOSFETs also in the thermally unstable portion of their transfer-characteristic. In such conditions, current crowding phenomena and hot-spots are formed, which can initiate degradation of the devices and eventually lead to their catastrophic failure. In this work, basing on the analysis of the cross-section of a failed chip, an interpretation of the evolution of the failure mechanism is presented. In particular, the conditions which characterise and define the failure itself are identified.

Partial Discharge Failure Analysis of AlN Substrates for IGBT Modules

J.-H. Fabian, S. Hartmann, A. Hamidi
ABB Switzerland Ltd, Corporate Research, CH-5405 Baden-D„ttwil, Switzerland

Increasing operating voltages of Insulated Gate Bipolar Transistor (IGBT) modules results in higher demands on the electrical insulation as well as partial discharge resistance. The most critical component is the ceramic substrate, which electrically insulates the high voltage side with the IGBT chip from the ground potential of the heat sink. Investigations on the Partial Discharge (PD) failures on the ceramic level as well as Phase Resolved Partial Discharge (PRPD) measurements have been performed and the distribution of the inception voltages for one substrate type analyzed. Electrical field simulations and optical discharge visualization are used for partial discharges localization. The edges of the copper metallization as well as voids at the ceramic-copper interface are identified as major PD sources

Investigation of IGBT turn-on failure under high applied voltage operation

Masayasu Ishiko^a*, Koji Hotta^b, Sachiko Kawaji^a, Takahide Sugiyama^a, Tomoyuki Shouji^a, Takeshi Fukami^b, Kimimori Hamada^b
a Power Device Lab., Toyota Central R&D Labs., Inc., Nagakute, Aichi, 480-1192, Japan
^b Electronics Engineering Div. III, Toyota Motor Corporation, Nishihirose, Toyota, 470-0309, Japan

In this paper, a new failure mode of punch-through type insulated gate bipolar transistors (PT-IGBTs) at short circuit condition under high voltage operation has been presented. After turning on the IGBTs, this failure mode is characterized as an abrupt destruction mode that takes place several microseconds later under higher collector voltage short circuit conditions. The destruction mechanism of the IGBTs has been investigated using a 2-D and a 3-D device simulation. It is found that the hole-current caused by dynamic avalanche generation at the peripheral region of the device leads to concentrate on a certain point such as the emitter contact edge of the active cells. Subsequently the IGBTs plunge into destruction. This hole-current aggregation depends on geometrical structure of the active cells close to the device peripherals where a parasitic PMOS is formed. The generated hole-current path is varied by the gate voltage and this effect results in degradation of the short circuit capabilities depending on the gate voltages. This model has been evaluated experimentally by making punch-through type IGBTs with a rating current of 200A and the IGBTs have shown enough short circuit capabilities. These devices have successfully been adopted as power devices of invertors for a new hybrid vehicle.

High reliable high power diode for welding applications

P. Cova^a, F. Fasce^b, P. Pampili^b, M. Portesine^b, G. Sozzi^a, P.E. Zani^b
a Dipartimento di Ingegneria dell'Informazione, University of Parma
Parco Area delle Scienze, 181/A - 43100 Parma, Italy
^b POSEICO S.p.A, via N. Lorenzi, 8 - 16152 Genova, Italy

Long-term power cycling of high power diodes for welding application is presented. The devices are packaged in an ultra-slim flat package, which allows very high heat sinking capability and rating current. Tests with different operating conditions were carried out and the results compared with the few data available in literature. Our devices show very good lifetime, especially considering that all tests were terminated without any performance degradation. Finally a thermo-electrical model of the device was built and will be used for both validation of lumped element thermal models and evaluation of new design solutions.

Analysis and optimisation through innovative driving strategy of high power IGBT performances/EMI reduction trade-off for converter systems in railway applications

G. Busatto^a, L. Fratelli ^b, C. Abbate^a, R. Manzo^a, F. Iannuzzo^a
a Dept. of Automation, Electromagnetism, Information Engineering and Industrial Mathematics,
University of Cassino Via G. Di Biasio, 43, 03043 Cassino (FR) - Italy
^b AnsaldoBreda Spa, via Argine, 425, 100147 Napoli - Italy

In railway applications possible interaction between power train and signalling system requires efforts to Electro Magnetic Compatibility (EMC) problems. With the progress of power device technology in recent years, it has become feasible to improve performances of power electronics systems; however EMI noise, caused by fast switching commutations in power converters, has to be managed. EMC control has, therefore, become a worldwide topic, and requests for EMI noise reduction have become very strong. In the paper, after a deep analysis of EMC features in railway applications, two innovative driving strategies have been introduced and characterized, in order to find a good trade-off between high power IGBT performances and EMI reduction constraints. Characterization and discussion are based on experimental basis.

The study of TDDB lifetime estimation for thin gate dielectrics
(INVITED, Best Paper Award RCJ Symposium)
Takeshi Shigeo, Kazuhiko Suzuki, and Madoka Muta
System LSI Reliability Eng. Gr. System LSI Quality & Reliability Eng. Dept. Toshiba Semiconductor Company

We have examined which distribution (weibull or log-normal) is suitable for Time-Dependent Dielectric Breakdown (i.e., TDDB) failure of thin (2.3 nm) and thick (6 nm) gate dielectrics. Through the constant voltage TDDB experiments and fitting of the data with regression analysis, we have found that log-normal is suitable for thin dielectrics, while weibull is well fitting for thick dielectrics.

Mie-Grüneisen Analysis of the Molecular Bonding States in Silica Which Impact Time-Dependent Dielectric Breakdown

J.W. McPherson
Silicon Technology Development, M/S 3740 , Texas Instruments, Inc., Dallas, Texas 75243

An effective molecular dipole-moment of 7-13eÅ is routinely observed during time-dependent dielectric breakdown (TDDB) testing of silica-based dielectrics. This rather narrow range of values is independent of oxide thickness, oxide test area, electrode materials, polarity, test temperature and oxide-growth conditions and strongly suggests a fundamental molecular property. A Mie-Grüneisen analysis of the molecular bonding states indicates that the upper-end of the effective dipole-moment range (13eÅ) is associated with a stretched silicon-oxygen bond while the lower-end (7eÅ) is consistent with a hole-captured silicon-oxygen bond. This would serve as molecular evidence that both current and field play important roles in TDDB.

Extraction of the trap distribution responsible for SILCs in MOS structures from measurements and simulations of DC and noise properties

A.Nannipieri^a,b, G. Iannaccone^b, F. Crupi^c
a ISE Integrated Systems Engineering AG, Affolternstrasse 52, CH-8050 Zurich, Switzerland
^b Dipartimento di Ingegneria dell'Informazione: Elettronica, Informatica,Telecomunicazioni,
Universita' degli Studi di Pisa and IEIIT-CNR, Via Caruso, I-56122 Pisa, Italy
^cDipartimento di Elettronica, Informatica e Sistemistica, University of Calabria, Italy

In this paper we present a detailed investigation of the properties of SILCs through MOS capacitors, focusing our attention on the extraction of the trap distribution from DC and shot noise properties of the structure. Our model of SILCs, based on inelastic Trap-Assisted Tunneling, is able to reproduce both the J-V characteristics and the shot noise suppression, explaining the latter in terms of Pauli Exclusion Principle and Coulomb repulsion. Fitting of numerical results with J-V characteristics before and after stress led to the extraction of distributions of native traps and stress-induced traps, respectively. In order to extract a unique trap distribution, comparison with shot noise measurements revealed to be mandatory. The combined effect of the two types of traps explains the DC and noise properties for the range of oxide thickness comprised between 4 nm and 10 nm, in which SILCs play a dominant role.

Plasma Charging Damage Reduction in IC Processing by A Self-balancing Interconnect

Z. Wang^a,b J. Ackaert^b, C. Salm ^a, F. G. Kuper^a,b, E. De Backer^b
a MESA+ Research Institute / University of Twente, Semiconductor Components Group
P.O. Box 217,7500 AE Enschede, The Netherlands
^b AMI Semiconductor, Westerring 15, B-9700 Oudenaarde,Belgium

In this paper, a novel first order self-balancing interconnect layout design is proposed for reducing plasma-process induced charging damage (P2ID) in modern CMOS processes. According to the mechanism of P2ID, dense interconnect lines collect positive charges due to electron shading (ES) effect [1] while sparse interconnect lines collect negative charges due to extended electron shading effect (EES) [2]. If the layout of the interconnect lines is such that the spacing between the interconnect lines is alternately wide and narrow both negative and positive charges are collected. Because these charges balance each other, the P2ID is reduced.

Effect of Pre-Existing Defects on Reliability Assessment of High-K Gate Dielectrics

G. Bersuker, J. H. Sim, C. D. Young, R. Choi, P. M. Zeitzoff, G. A. Brown, B. H. Lee, R. W. Murto
International SEMATECH, Austin, TX 78741

Response of the high-k gate dielectrics to low voltage stresses was studied by probing high-k transistors with various voltage/time measurements at different temperatures. The observed dependence of the transistor threshold voltage on stress time was attributed to electron trapping at pre-existing defects in the high-k dielectric rather than stress-induced trap generation. The dominance of the contribution from the reversible electron trapping on the pre-existing defects in the low voltage stress response raises the question on the applicability of the conventional reliability assessment methodology to the high-k dielectrics.

Reliability of High-K Dielectrics and Its Dependence on Gate Electrode and Interfacial / High-K Bi-Layer Structure

Y. H. Kim**, R. Choi, R. Jha*, J.H. Lee*, V. Misra*,and J. C. Lee
Microelectronics Research Center, Department of Electrical and Computer Engineering
The University of Texas, Austin, TX 78758
* Dept. of ECE, North Carolina State University, Raleigh NC 27695
** now with IBM, Yorktown Heights NY 10598


In this work, we present the reliability of HfO₂ and how it depends on the barrier height and the nature of the bi-layer structure. We will also discuss how these factors lead to different charge fluence, charge-to-breakdown, and breakdown characteristics. It is found that the lower Weibull slope of high-k dielectrics is partially attributed to high charge fluence by the lower barrier height of high-k dielectrics, and a different nature of bi-layer structure. In addition, it has been found that there is distinct bi-modal defect generation rate for high-k/SiO₂ stack. A two-step breakdown process was clearly observed. Soft breakdown characteristics were dependent on the barrier heights. It is attributed to different charge fluence by different barrier heights. Charge-to-breakdown shows strong barrier height dependence.

Implementation of TRE systems into Emission Microscopes

A. Tosi^a, M. Remmach^b, R. Desplats^b, F. Zappa^a, P. Perdu^b
a Politecnico di Milano, Dipartimento di Elettronica e Informazione
^b CNES- French Space Agency - 18 avenue Edouard Belin - 31401 Toulouse Cedex 9 - France

Time-Resolved photon Emission (TRE) has the potential to identify faults by analysing the luminescence emission, as a function of time. TRE detectors provide time capabilities, but they have the disadvantage to be a single-point measurement, with no possibility to spatially map the luminescence emissions from the chip. In order to first localize the luminescence origin (e.g. a switching transistors or a faulty device within a chip), it is interesting to couple TRE equipments (i.e. time information) with light emission microscopes (i.e. spatial information). In this paper, we present a quantitative comparison of various commercially-available TRE detectors and photon counting electronic modules. From the analysis of the best solution, we propose a cost effective solution for the implementation of a TRE detector into a commercial emission microscope, with no hardware modifications.

Overcoming Fault Test Coverage with Time-Resolved Emission (TRE) Probing

Steven Kasapi^a and Bruce Cory ^b
a Credence Systems Corporation, 1421 California Circle Milpitas, CA 95035
^b NVIDIA Corporation, 2701 San Tomas Expressway, Santa Clara, CA 95050

We discuss an approach to combining internal logic waveform measurements with automated test pattern generation (ATPG) tools. The internal logic waveform measurements, provided by time-resolved emission (TRE) technology, localized the root-caused of a failure that was ambiguous from the ATPG analysis alone.

New trends in the application of Scanning Probe Techniques in Failure Analysis

T. Schweinböck ^a, S. Schömann ^a, D. Alvarez ^a,b, M. Buzzo ^c,d, W. Frammelsberger ^e,f, P. Breitschopf ^e, G. Benstetter
^a Infineon Technologies AG, München, Germany
^b IMEC, Leuven, Belgium
^c Infineon Technologies AG, Villach, Austria
^d Swiss Federal Institute of Technology (ETH), Integrated Systems Laboratory, Zurich, Switzerland
^e University of Applied Sciences Deggendorf, Deggendorf, Germany
^f University of the West of England, Bristol, UK

This contribution gives an overview of new developments in the field of Scanning Probe Techniques in semiconductor Failure Analysis. It will focus on Scanning Capacitance Microscopy (SCM) and Spectroscopy (SCS) as well as Scanning Spreading Resistance Microscopy (SSRM) for implant mapping and Conducting AFM (C-AFM) for characterization of dielectric layers. Examples for an improved characterization and localization of p-n junctions using SCS are presented. It is shown how high resolution and quantitative information of doping and conductivity may be obtained by SSRM. Furthermore, examples are given how C-AFM measurements may be extended towards ultra thin (below 3 nm) and thick (more than 100 nm) oxide layers and how oxide thickness may be modelled in an easier way.

Quantitative 3D reconstruction from BS imaging

R. Pintus, S. Podda, F. Mighela and M. Vanzi
University of Cagliari,-INFM- Department of Electrical and Electronic Engineering, Cagliari, Italy

The well known technique for separately enhancing topographic and compositional contrast in BS images has been refined. The underlying quantitative theory has been developed, both for acquisition and processing, and tested first in the optical field. The surprisingly good results moved to return to the SEM and to transfer the whole procedure from light to Back Scattered electron images. The preliminary results strongly address for future developments, even for microelectronics, pointing towards FEG SEM operation.

Automated Diagnosis and Probing Flow for Fast Fault Localization in IC

D.Martin^a, R.Desplats ^b, G.Haller^a, P.Nouet^c, F.Azaïs^c
aST Microelectronics, Z.I. de Rousset, 13106 Rousset, France
^bCNES laboratory - bpi 141418, avenue Edouard Belin, 31401 Toulouse, France
^cLIRMM, Universit‰ Montpellier II / CNRS, 161 Rue Ada, 34392 Montpellier Cedex 5, France

The continually increasing complexity of integrated circuits has made fault localization progressively more difficult. Despite significant improvements in test and diagnosis tools, probing is still required for acquiring new information and for confirming test results. For this reason, we have developed an optimized diagnosis-to-probing flow which significantly reduces the number of nodes to be probed and which dramatically cuts the cost of fault localization. With this approach, probing can be integrated in test and diagnosis operations to reach nodes which are known to be untestable.

Magnetic Microscopy for IC Failure Analysis: Comparative Case Studies using SQUID, GMR and MTJ systems

Olivier Crépel^a, Patrick Poirier^a, Philippe Descamps^a, Romain Desplats^b, Philippe Perdu^b, Gérald Haller^c, Abdelhatif Firiti^c
aLaMIP, Philips Semiconductors, 2 rue de la Girafe 14079 Caen Cedex, France
^bCNES- French Space Agency, 18, avenue Edouard Belin 31401 Toulouse, France
^cST Microelectronics, ZI de Rousset 13106 Rousset, France

Magnetic field based techniques have shown great capabilities for investigation of current flows in ICs. After reviewing the performances of SQUID, GMR (hard disk head technologies) and MTJ existing sensors, we will present results obtained on various case studies. This comparison will show the benefit of each approach according to each case study (packaged devices, flip-chip circuits, ...). Finally, from the obtained results we classify techniques, their optimal domains of application and benefits.

Study on electrostatic discharge (ESD) reliability improvement of ZnO-based multilayered chip varistor(MLV)

M. H. Ji *, C. H. Choi, B. K. Jang, B. K. Kim
Central R&D Institue, Samsung Electro-Mechanics Co. Ltd, 314, Maetan 3-Dong, Yongtong-Gu, Suwon, Korea

An improvement of electrostatic discharge (ESD) reliability in a ZnO-based multilayered chip varistor (MLV) has been studied using transmission electron microscopy (TEM), energy dispersive x-ray spectroscopy (EDX) and micro x-ray diffraction (XRD). A sample including a small amount of Si shows the remarkable improvement of ESD reliablility when compared to a sample fabricated without Si. It is found that the Si-added sample can withstand even under 25KV ESD. In order to understand this outstanding result, overall microstructure of a MLV is investigated by TEM. EDX line profiles in TEM reveal that the small amount of Si coexists with Bi-rich phase along grain boundaries (GBs). Results of high resolution (HR) TEM micrographs show that the crystalline phase in the triple points (TPs) is crystalline, whereas in the narrow GB regions the phase is amorphous. For understanding the phases in the TPs, the crystallography of BiOx phases is investigated by the micro-XRD in detail. From the micro-XRD measurement of a small size MLV (1.0mm x 0.5mm), the Bi₂₄Si₂O₄₀ (cubic, I23) and δ-BiO₃ phases are detected as well as a main phase in a MLV, zincite (Sb-rich spinel structure). As a result, the Bi₂₄Si₂O₄₀ phase is likely to be the Bi-rich crystalline phase found in the TPs by TEM analysis, and also the phase partially contributes to the improvement of ESD resistance. The addition of the small amount of Si may cause the phase transition in the thin amorphous BiOx of the GBs during sintering process. Therefore, it can be concluded that the controlling of additive elements in a MLV results in a major effect of an improvement on the ESD reliability in a MLV.

Fail / Recover / Fail (F/R/F) failure mechanisms new trend

C. Ali(a)*, C. Charpentier(a)
Texas Instruments France, NDAL, av. Jack Kilby BP5 06270 Villeneuve-Loubet - France

The need to improve the failure analysis results accuracy and the cycle time reduction of all the reliability and qualification is a key factor of the success for new products or technologies. The 150°C bake during the failure analysis process is known to segregate the failure mechanisms. All the recovered units submitted to the reliability test duplication have not the same behavior. The F/R/F (Fail/Recover/Fail) delay failure duplication leads to the failure mechanisms. The study of this delay versus failure mechanisms found during several EFR (Early Failure Rate) exercises is presented.

Negative Bias Temperature Instability in Triple Gate Transistors
(INVITED, Best Paper Award IRPS)
Shigenobu Maeda, Jung-A Choi, Jeong-Hwan Yang, You-Seung Jin, Su-Kon Bae, Young-Wug Kim, and Kwang-Pyuk Suh
Technology Development Team, System LSI Division, Samsung Electronics
San #24 Nongseo-Ri, Giheung-Eup, Yongin-City, Gyeonggi-Do, Korea 449-711

Negative bias temperature instability (NBTI) in triple gate transistors was investigated for the first time. It is found that the threshold voltage shift caused by negative bias temperature stress in conventional configuration of triple gate transistors is worse than that in planar transistors. This is due to the larger trap state density of the {110} side surface of the active silicon and it is verified by comparing two types of triple gate transistors each of which has {110} side surface and {100} side surface. The ⟨100⟩-direction channel is proposed as one of the structural options to reduce the degradation of NBTI in triple gate transistors.

Evidence for source side injection hot carrier effects on lateral DMOS transistors

S. Aresu², , W. De Ceuninck^1,2, G. Van den bosch³, G. Groeseneken^3,4, P. Moens⁵, J. Manca^1,2, D. Wojciechowski⁵, P. Gassot^5
1Limburgs University Centre, Institute for Materials Research, Wetenschapspark 1, B-3590 Diepenbeek, Belgium
² IMEC vzw, division IMOMEC, Wetenschapspark 1, B-3590 Diepenbeek, Belgium
³ IMEC vzw, Kapeldreef 75, B-3001 Heverlee, Belgium
⁴Katholieke Universiteit Leuven, ESAT Departments, Leuven, Belgium
⁵AMI Semiconductor Belgium BVBA, Westerring 15, B-9700 Oudenaarde (Belgium)

The hot carrier degradation behavior of lateral integrated DMOS transistors is studied in detail with a state-of-the-art, high-resolution measurement equipment. It has been demonstrated that two degradation mechanisms are present: electron mobility reduction due to interface trap formation and injection and trapping of hot electrons at the source side of the channel. It will be shown that the Source Side Injection mechanism gives rise to rather moderate changes of the linear drain current (I_d,lin) but significant changes of the saturation drain current (I_d,sat) and the threshold voltage (V_t).

Locating hot carrier injection in n-type DeMOS transistors by Charge Pumping and 2D device simulations

F. Bauwens and P. Moens
Technology R&D. AMI Semiconductor Belgium BVBA, Westerring 15 9700 Oudenaarde, Belgium

The hot carrier degradation behaviour of a drain extended MOS device is presented in this paper. It is shown that upon reverse bias stress interface states (Dit) are created in the channel as well as in the spacer region, the latter being the dominant mechanism. Combining hot carrier and charge pumping experiments and 2D device simulations, the origin and location of degradation can be determined. Hot electron injection is localised well into the spacer, leading to a degradation in on-resistance (Ron). Only 10 % of these injected electrons form interface states. For low Vgs, injection (and degradation) is highest, and a smaller amount of hole injection at the poly edge shows up. For high Vgs or longer stress times, the electron injection shifts further into the spacer reducing the degradation effect.

Effects of hot carrier and irradiation stresses on advanced excimer laser annealed polycrystalline silicon thin film transistors

D.N. Kouvatsos^a, V. Davidovic^b, G.J. Papaioannou^c, N. Stojadinovic^b, L. Michalas^c, M. Exarchos^c, A.T. Voutsas^d and D. Goustouridis^a
a Institute of Microelectronics, NCSR Demokritos, Aghia Paraskevi 153 10, Greece
^b Faculty of Electronic Engineering, University of Nis, Beogradska 14, 18000 Nis, Serbia and Montenegro
^c Solid State Section, Physics Department, University of Athens, Panepistimiopolis Zografos, 157 84, Greece
^d LCD Process Technology Laboratory, Sharp Labs of America, Inc., 5700 NW Pacific Rim Boulevard, Camas, Washington 98607, USA

The effects of hot carrier and gamma-irradiation stresses on thin film transistors fabricated in polysilicon films crystallized using the advanced sequential lateral solidification excimer laser annealing (SLS ELA) process, as well as the polycrystalline silicon film quality, are investigated. The TFT drain current transients after a gate bias pulsing in the OFF state were similar at room temperature at dark or under illumination and exhibited a marked fall, due to generation freezeout, at cryogenic temperatures. This behavior is indicative of low defect density and good crystal quality. The application of DC hot carrier stress, with a condition of V_GS = V_DS/2, was found to induce threshold voltage, subthreshold slope and electron mobility degradation, which, for all these parameters, is significantly higher for thicker polysilicon films. A stress condition with higher vertical field resulted in increased Vth shift but decreased s and μ degradation. The γ-irradiation of the ELA TFTs resulted in a negative V_th shift, which is higher for thicker polysilicon films, and a small s and degradation, while the oxide and interface charge densities increased.

Effects of hot carrier stress on the RF performance in SOI MOSFETs

Byung-Jin Lee, Kyosun Kim, and Jong-Tae Park
Department of Electronics Engineering, University of Incheon
#177 Dohwa-dong Namgu, Inchon, 402-749, Korea

This paper presents new experimental results on the DC hot carrier stress effects on the RF performance of SOI MOSFETs. The RF performance degradation in terms of cut-off frequency, minimum noise figure, and RF power has been measured and analyzed. The reduction of transconductance is turned out to be one of the major causes of the RF performance degradation. The measurement also shows that the RF performance degradation is more significant than the DC performance degradation. Especially, the degradation of minimum noise figure is the most significant.

Time Resolved Photon Emission Processing Flow for IC Analysis
(INVITED)
R. Desplats^a, G. Faggion^a, M. Remmach^a, F. Beaudoin^a, P. Perdu^a, D. Lewis^b
aCNES-Thales lab. French Space Agency, 18, avenue Edouard Belin 31401 Toulouse - France
^bIXL Laboratory, 351 cours de la Libération, 33405 Talence Cedex - France

IC analysis can be facilitated using Time Resolved Photon Emission (TRE). Because recent technologies work at ultra low power supply voltages: <1V, background noise can mask commutation peaks thus biasing analyses. With a positive photon discrimination flow, signals can be extracted even below the noise level. However signal extraction depends on various parameters (e.g., bin size, cutoff frequency). WE have developed a photon discrimination technique to optimize these parameters. This technique is integrated into a generic method which takes advantage of static light emission acquisition for identifying switching transistors and which links TRE measurements to simulations for optimal IC diagnostics.

Testing of Ultra Low Voltage VLSI Chips using the Superconducting Single-Photon Detector (SSPD)

Franco Stellari and Peilin Song
IBM T.J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, NY 10598, USA

In this paper we discuss the use of the Superconducting Single-Photon Detector (SSPD) in the framework of the Picosecond Imaging Circuit Analysis (PICA) technique for testing chips by extracting electrical waveforms, propagation delays and skews. An IBM microprocessor fabricated in a 0.13 µm technology with 1.2 V nominal supply voltage V_DD will be used as a benchmark for characterizing the detector and evaluating its applicability to future technologies with low V_DD and high frequency clocks.

Interactive and non-destructive verification of SRAM-descrambling with laser

A. Stuffer
Department of Failure Analysis, Infineon AG, Munich

Sram-Analysis is important for all new technological issues, especially during ramp up. A problem for those analysis approaches is to know the exact physical location of a given logical failing address. In this case, the verification of sram-descrambling is absolutely necessary and can be a real challenge. Especially large designs with big sram parts or many sram-blocks are scrambled to ensure the functionality, easy layouting and logical word addressing. The most easiest, accurate, fastest and non destructive solution is the verification of the descrambling-routines with the LVP (Laser Voltage Prober) or other laser methods with the possibility to point the laser to one specific location due to resolution-issues

Understanding the effects of NIR Laser Stimulation on NMOS transistor

A. Firiti^a, F. Beaudoin^b, G. Haller^a, P. Perdu^b, D. Lewis^c, P. Fouillat^c
a ST Microelectronics, 13106 Rousset, France
^b CNES-Thales laboratory - Bpi 141418, avenue Edouard Belin, 31401 Toulouse, France
^c IXL Laboratory, ENSEIRB, Université Bordeaux 1, 351, Cours de la Lib‰ration, 33405 Talence, France

NIR laser stimulation techniques allow localizing defects on integrated circuits from frontside and backside. At times, the understanding of signatures given by theses mapping techniques appears not easy. Their interpretations are often referenced from sample structures such as metal lines and p-n junction. A study of laser stimulation effect on elementary transistors seems to be necessary. This work presents a detailed investigation of thermal and photoelectrical laser influence on a single NMOS transistor. The main purpose is to understand and quantify NIR laser stimulation effects.

2D Dopant Profiling on 4H Silicon Carbide P+N Junction by Scanning Capacitance and Scanning Electron Microscopy

Marco Buzzo^1,2, Markus Leicht¹, Thomas Schweinböck³
Mauro Ciappa², Maria Stangoni² , Wolfgang Fichtner²
(1) Infineon Technologies AG, Villach, Austria
(2) Swiss Federal Institute of Technology (ETH), Integrated Systems Laboratory, Zurich, Switzerland
(3) Infineon Technologies AG, Munich, Germany

This paper proposes a comparison between a 2D dopant analysis of a 4H Silicon Carbide p+n-junction carried out by Scanning Capacitance (SCM) and by Scanning Electron Microscopy (SEM). Two samples prepared both by cleaving and by polishing are investigated to quantify the impact of the surface roughness on the SCM signal. The properties of the native oxide grown on the SiC samples are characterized by the use of Conducting Atomic Force Microscopy and its suitability as a dielectric layer for SCM is discussed. The 1D-profiles, as extracted by SCM and SEM are finally compared with simulations and with Secondary Ion Mass Spectroscopy data.

Transient interferometric mapping of smart power SOI ESD protection devices under TLP and vf-TLP stress

S. Bychikhin^a, V. Dubec^a, D. Pogany^a, E. Gornik^a, M. Graf^b, V. Dudek^b, W. Soppa^c
a Institute for Solid State Electronics, Vienna University of Technology, Floragasse 7, A-1040 Vienna, Austria
^b Atmel Germany GmbH Theresienstraße 2, 74025 Heilbronn, Germany
^c FH Osnabrück, FB Elektrotechnik, Albrechtstraße 30, 49076 Osnabrück, Germany

Smart power SOI technology electrostatic discharge (ESD) protection devices are investigated under the transmission line pulser (TLP) and very-fast TLP stress. Thermal and free carrier distributions in the Si active layer during the stress are measured by transient interferometric mapping (TIM) method. It is shown that in contrast to measurements in bulk structures, the TIM phase signal in SOI structures is affected by multiple reflections within the Si active layer. The influence of the thickness of the Si active and oxide layers on the phase signal is investigated by optical matrix simulation. The triggering homogeneity, hot spots and carrier injection places are analysed in devices with a circular and linear geometry and correlated with results of device simulation.

A laser-based instrument for measuring strain in electronic packages using coherent fibre-bundles

Peter Dias-Lalcaca^a, , Erwin Hack^a, Filippo Visintainer^b, Stefano Bernard^b, Urs Sennhauser^a
a Swiss Federal Laboratories for Materials Testing and Research (EMPA),
Electronics / Metrology Lab, Ueberlandstrasse 129, CH-8600 Duebendorf, Switzerland
^b Centro Ricerche Fiat, CRF - Unità Operativa Trento, Via dei Solteri 38, I-38100 Trento (TN), Italy

Thermal and mechanical stresses induced by the reflow soldering process or by operating conditions can adversely affect the reliability of microelectronic devices. A prototype instrument based on electronic speckle pattern interferometry (ESPI), developed at EMPA as part of the HIRONDELLE project, is intended to measure the strain fields developed in BGAs and similar devices under thermal load. The instrument uses an NIR laser diode source coupled to a special optical delivery system to illuminate the device under test as it is subject to thermal loading. Coherent fibre bundles are used to transfer the images of the BGA to the object plane of the camera. We report on the measurement system and first tests performed on solder joint arrays.

Localization of FET Device Performance with Thermal Laser Stimulation

Sanjib K. Brahma, Christian Boit, Arkadiusz Glowacki, H. Suzuki*
Berlin University of Technology, Einsteinufer 19, Sekr. E2, D-10587 Berlin, Germany
* Hamamatsu Photonics K.K., Japan

Thermal Laser Stimulation (TLS) is applied for various localization techniques on metal interconnects, but it can also increase channel resistivity in FETs. quantitative measurements prove how this effect can be produced by laser beam absorption of free carriers in silicon. The light to heat conversion efficiency is much more in a metal interconnect though. It is demonstrated how TLS of a nearby interconnect by its heat diffusion to the FET can produce an even higher temperature shift in the channel area. The corresponding diffusion properties have been derived from the results.

Degradation of electrical performance and floating body effect in ultra thin gate oxide FD-SOI n-MOSFETs by 7.5-MeV proton irradiation

K. Hayama^a,*, K. Takakura^a, H. Ohyama^a, A. Mercha^b E. Simoen^b, C. Claeys^b,c, J.M. Rafí^d and M. Kokkoris^e
Kumamoto National College of Technology, 2569-2 Nishigoshi, Kumamoto 861-1102, Japan
^b IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
^c also at E.E. Dept, KU Leuven, Belgium
^d Institut de Microelectrònica de Barcelona (CNM-CSIC), Campus UAB, 08193 Bellaterra, Spain
^e Institute of Nuclear Physics, Tandem Accelerator, NCSR 'Demokritos' 153 10 Aghia Paraskevi, Athens, Greece

The degradation of the electrical performance of ultra thin gate oxide fully depleted (FD)-SOI n-MOSFETs subjected to 7.5-MeV proton irradiation is reported. The degradation is investigated by studying the static characteristics of transistors with different geometries and back-gate bias conditions. Special attention is paid to the analysis of the floating body effect induced by the application of an accumulation bias to the back-gate. It is shown that the degradation is more pronounced for short channel transistors. The subthreshold swing for the front and back channel are examined for devices with different L and VBG. The hysteresis characteristics of the drain and gate current, and the drain current transients are examined as well.

Reliability Evaluation and Redesign of LNA

Wei-Cheng Lin, Long-Jei Du, Ya-Chin King
Microelectronics Laboratory, Semiconductor Technology Application Research (STAR) Group,
Department of Electrical Engineering, National Tsing-Hua University, Hsin-Chu 300, Taiwan
Phone/Fax: +886-3-5715131-4107/ +886-3-5721804, E-mail: d895028@oz.nthu.edu.tw

A device degradation model reported in our previous work is used for circuit-level reliability evaluation. The sub-circuit model can successfully describe both the DC and AC device degradation characteristics under hot-carrier stress. An analysis on Low Noise Amplifier (LNA) vulnerable to hot carrier is discussed and evaluated. The circuit performance degradation predicted by this sub-circuit model shows fairly good agreement with measurement results

Creep as a reliability problem in MEMS

R. Modlinski^1,2, A. Witvrouw¹, P. Ratchev¹, A. Jourdain¹, V. Simons¹, H.A.C. Tilmans¹, J.M.J. den Toonder³, R. Puers² and I. De Wolf^1
1IMEC vzw, Kapeldreef 75, B-3001, Leuven Belgium,
²E. E. Dept of K. U. Leuven, Leuven, Belgium,
³Philips Research Laboratories, Eindhoven, The Netherlands

Creep is expected to be one of the major reliability problems for certain MEMS. In particular RF-MEMS switches with metal bridges will be endangered, especially at high RF power, if the bridge material is not selected appropriately. In this paper, substrate curvature measurements are used to study creep properties of Al, Al_98.3Cu_1.7, Al_99.7V_0.2Pd_0.1 and Al_93.5Cu_4.4Mg_1.5Mn_0.6 films using isothermal tensile stress relaxation. For all aluminum compositions dislocation glide describes the relaxation data very well up to 110°C. However a large difference in creep sensitivity is measured: Al_93.5Cu_4.4Mg_1.5Mn_0.6 is the alloy that is most resistive to creep. We propose a very simple way of characterizing Al alloy thin films by two creep parameters: activation energy ΔF and athermal flow stress τ. We also show a direct relation between the parameters and the coherence, size and spacing of precipitates observed by SEM and TEM in the alloys. In addition we report that neither heating rates nor maximum temperatures (above 200°C) have an influence on stress in pure Al films.

Impact of the space environmental conditions on the reliability of a MEMS COTS based system

P. Schmitt^a,b, X. Lafontan^c, F. Pressecq^a, B. Kurz^a, C. Oudea^d, D. Estève^b, J.Y. Fourniols^b, H. Camon^b
a CNES, bpi 1414, 18, Av. E. Belin, 31401 Toulouse Cedex 9, France
^b LAAS - CNRS, 7, Av. Col. Roche, 31077 Toulouse Cedex 4, France
^c Nova MEMS, 14 rue du quai, 09700 Saverdun, France
^d EADS - ST, 66, route de Verneuil, 78133 Les Mureaux Cedex, France

Commercial-off-the-shelf (COTS) micro-electromechanical systems (MEMS) have attractive properties for space applications (lightweight, ...), but before using them reliability aspects have to be considered. MEMS COTS are components developed for mass markets and are so in general intended for applications on earth. They have thus only been tested for this type of application and before using them in space, their reliability must be assured in the harsh space environment (radiation,...). The presented reliability approach combines technological analyses, environmental testing and modeling techniques. It has been applied to a specific case: the part of a launch vehicles measurement system has been modeled as a virtual prototype and different MEMS models (accelerometers, pressure sensors...) can be inserted into this model. By the mean of simulation the impact of environmental constraints can be evaluated for a specific mission. In our case we have inserted a COTS accelerometer model, the ADXL150. The influence of two environmental constraints, humidity and radiation, has been considered.

Experimental measurements and 3D simulation of the parasitic lateral bipolar transistor triggering within a single finger gg-nMOS under ESD

P.Galy1, V.Berland1,2, A.Guilhaume3, F.Blanc4, J.P.Chante5
1 Pole Universitaire Leonard de Vinci, 92 916 Paris la Defense, France 2 LORE, 104 Av. du President Kennedy, 75 016 Paris, France 3 EADS CCR, Centre Commun de Recherche, BP 76, 92 152 Suresnes, France 4 PHILIPS Semiconductor, 2 rue de la girafe, BP 5120, 14 079 Caen, France 5 CEGELY INSA Lyon, Bat. 401, 20 av. A. Einstein, 69 621 Villeurbanne, France

The aim of this study is to propose an analysis of the parasitic lateral bipolar triggering into a single finger grounded gate n-MOS transistor under Transmission Line Pulse (TLP) stress. The experimental values are compared to numerical results issued from 3D simulation. Emission Microscopy for Multi-layer Inspection (EMMI) views and physical extractions for analysis during this electrical stress reveal similar results. Thus, it appears that the triggering is different for two ElectroStatic Discharge (ESD) current levels.

Low Frequency Noise Measurements for ESD Latent Defect Detection in High Reliability Applications

N. Guitard^a, D. Trémouilles^a, M. Bafleur^a, L. Escotte^a, L. Bary^a, P Perdu^b, G. Sarrabayrouse^a, N. Nolhier^a, R. Reyna-Rojas^b
aLAAS/CNRS, 7, avenue du Colonel Roche - 31077 Toulouse Cedex 4, France
^bCNES, 18 avenue Edouard Belin - 31041 Toulouse Cedex 4- France

To increase the reliability of embedded systems and more particularly in high reliability applications such as the aerospace application, it is important to guarantee that the integrated parts are free of any defect. To achieve this goal, one way consists of screening parts before their integration. In this paper, low frequency noise (LFN) measurement is proposed as a method to detect that a circuit underwent an ESD stress. Potentialities of this technique are assessed on a simple device, a GCNMOS ESD protection and a digital circuit. [Keywords: ESD, latent defect, low frequency noise, S-Parameter, GCNMOS]

Electrostatic Effects on Semiconductor Tools

P. Jacob^a,b, J. C. Reiner^a
a EMPA Swiss Federal Laboratories for Materials Testing and Research, Duebendorf, Switzerland
^b EM Microelectronic Marin SA, Rue des Sors 2-3, CH-2074 Marin, Switzerland

The paper describes physical details of process-tool-induced surface ESDFOS (Electrostatic Discharge From Outside-to-Surface). In many post-wafer processes, electrostatic discharge takes place by charged handlers, chip pickers etc. Or, on the other hand, singular devices suffered charging on blue foil, carrier tapes, etc. In all these cases, the discharge impact breaks through the passivation and destructs the device surface; in most cases, short-circuits between the two top metal layers result. The mechanism and its latency risk is described well in a recent publication of JMR. This paper now shows the different grades of discharge severeness, how to recognise best the failure mechanism and some estimations considering voltage and energy. Practical experience has shown that, over the whole branch, in many cases, a misinterpretation takes place, when visual inspections found such kind of failures: Most of them have been put into the category "Mechanical Damage" and thus, the root cause remains undiscovered.

Multiple-time-instant 2D thermal mapping during a single ESD event

V. Dubec^a, S. Bychikhin^a, M. Blaho^a, M. Heer^a, D. Pogany^a, M. Denison^b, N. Jensen^b, M. Stecher^b, G. Groos^c, E. Gornik^a
aInstitute for Solid State Electronics, Vienna University of Technology, A-1040 Vienna, Austria
^bInfineon Technologies, Balanstrasse 73, D-81617 Munich, Germany
^cUniversity of the Federal Armed Forces Munich, D-85577 Neubiberg, Germany

A 2D transient interferometric mapping (TIM) method for thermal and free carrier imaging of semiconductor devices at two time instants during a single electrical stress event is presented. The time resolution is 5 ns and the time delay between imaging laser pulses is independently adjustable. By using a short delay between the pulses, the instantaneous 2D density of dissipated thermal power can be calculated. The method is applied to investigate moving current filaments in smart power DMOS transistors and in electrostatic discharge (ESD) protection devices exhibiting non-repeatable triggering behaviour under ESD-like stress.

Reliability Challenges with Ultra-Low k Interlevel Dielectrics (INVITED)

J.R. Lloyd, M.R. Lane, X.-H. Liu, E. Liniger, T.M. Shaw, C.-K. Hu, R. Rosenberg
IBM T.J. Watson Research Center, Yorktown Heights NY 10598, USA

The adoption of ultra-low k dielectric materials in the pursuit of greater performance will pose reliability challenges quite unlike what we have previously experienced. The ultra-low k (ULK) dielectrics are completely different from the materials we have traditionally used. Unfortunately, the properties that make them desirable from an electrical point of view make them undesirable from a mechanical and environmental point of view. Low mechanical strength, low elastic modulus, rapid diffusion and susceptibility to dielectric breakdown are all characteristic of the ULK dielectrics. In this paper we review work we have performed in our laboratory to understand and characterize these new and temperamental materials.

Reliability Improvement in Al Metallization: A Combination of Statistical Prediction and Failure Analytical Methodology

G. Zhang^a, C. M. Tan^a, K. T. Tan^b, K. Y. Sim^b, and W. Y. Zhang^b
aDivision of Microelectronics, School of EEE, Nanyang Technological University, Singapore 639798
^b Department of Failure Analysis & Reliability, Systems on Silicon Manufacturing Co. Pte. Ltd., 70 Pasir Ris Drive 1, Singapore 519527

Failure mechanism identification in metal interconnect is an important step to appropriately improve the interconnect reliability characteristics. However, analysis of all the failed units from accelerated testing is too time consuming and impractical in industry. In this work, a statistical prediction combined with advanced failure analytical techniques is developed that can classify all the failed units into different failure categories simply based on their time to failure. Thereafter, detail failure analysis on only one or two failures within each category will be sufficient to identify the failure mechanisms of different categories. An industrial case is given to illustrate this analysis procedure. This approach also suggests that the early failure could be different under stress and normal use condition, and hence, care have to be taken when prioritize improvement action for field reliability improvement.

MTF test system with AC based dynamic joule correction for electromigration tests on interconnects

L. Biesemans ^a,c, K. Schepers ^a, K. Vanstreels ^a, J. D'Haen ^b, W. De Ceuninck ^a,b and M. D'Olieslaeger ^a,b
a Institute for Materials Research, Limburgs Universitair Centrum, Wetenschapspark 1, Diepenbeek, Belgium
^b IMEC vzw, division IMOMEC, Wetenschapspark 1, B-3590 Diepenbeek, Belgium
^c Hogeschool Limburg, Universitaire Campus, Gebouw H, B-3590 Diepenbeek, Belgium

For accelerated electromigration tests to be accurately measured and extrapolated, the sample temperature has to remain constant during the entire test. Conventional Median Time to Failure (MTF) test systems take the joule heating into account only at the beginning of the test, which is not sufficient. A solution to this problem was formulated by Scandurra et al. by introducing a DC-current based dynamic joule correction. In this paper, a new test system has been developed which makes use of an AC-current based dynamic joule correction. In this way, no electromigration effects take place during the determination of the thermal resistance.

An improved isothermal electromigration test for Cu-damascene characterization

M. Impronta ^a, S. Farris ^a, A. Scorzoni ^a,b
a Istituto per la Microelettronica e Microsistemi (CNR-IMM), Consiglio Nazionale delle Ricerche,
via P. Gobetti 101, 40129 Bologna, Italy, e-mail: maurizio.impronta@imm.cnr.it
^b Dipartimento di Ingegneria Elettronica e dell'Informazione, Università di Perugia,
via G. Duranti 93, 06131 Perugia, Italy, e-mail: scorzoni@diei.unipg.it

Wafer level accelerated tests are very attractive to characterize the reliability of Cu metallizations. In this work we deal with the isothermal electromigration test, introducing all the recent recommendations for a correct temperature determination, which is crucial for Cu-damascene structures. Also, we propose a procedure for an optimal convergence to the stress temperature. Promising results are shown.

Analysis of the layout impact on electric fields in interconnect structures using finite element method

Changsoo Hong ^a, *, Linda Milor ^a, MZ Lin ^b
a School of Electrical and Computer Engineering, Georgia Institute of Technology, 791. Atlanta, USA
^b Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, Taiwan, R.O.C.

The impact of layout on electric field is investigated using 2-D and 3-D field solvers based on the finite element method (FEM). It has been demonstrated that design layouts can greatly enhance the electric field intensity locally in critical regions. The effect of the vertical structure of the back end of line (BEOL) and the material properties of intermetal dielectrics (IMD) on electric field has also been covered. It has been demonstrated that the dielectric constants of IMD, and etch stop layer (ESL) do not affect the electric field intensity and distribution. New test structures will be proposed for improved breakdown analysis of BEOL structure.

Characterization of self-heating effects in semiconductor resistors during transmission line pulses.

C. Corvasce^a, M. Ciappa^a, D. Barlini^a, S. Sponton^b, G. Meneghesso^b, W. Fichtner^a
a Swiss Federal Institute of Technology, Integrated Systems Laboratory, CH-8092 Zurich, Switzerland
^b University of Padova, Department of Information Engineering, Via Gradenigo 6/B, 35131-Padova, Italy

The purpose of this work is the experimental extraction of the local average temperature occurring in silicon resistors when a transmission line pulse is applied. The local temperature is determined by combining transmission line pulses of different amplitude and at different ambient temperatures with three-dimensional electro-thermal simulation. The obtained calibration curves are applied to convert the phase shift information as obtained by interferometric techniques (e.g. in Transient Interferometric Mapping) into absolute temperature readings.

Statistical simulation of gate dielectric wearout, leakage, and breakdown

A. Gehring and S. Selberherr
Institute for Microelectronics, Vienna University of Technology Gußhausstraße 27-29, A-1040 Vienna, Austria

We present a set of models for the simulation of gate dielectric leakage, wearout, and breakdown. The leakage model accounts for direct and trap-assisted tunneling through the dielectric layer. Wearout is caused by the leakage-induced creation of neutral defects at random positions in the dielectric layer, which, if occupied, degrade the threshold voltage of the device. Gate dielectric breakdown is triggered by the formation of a conductive path through the insulator. To allow trap characterization and for the simulation of fast transients the modeling of trap charging and decharging processes is outlined. The models have been implemented into a threedimensional device simulator and are used for the characterization of ZrO₂-based dielectrics and for the study of gate leakage and wearout effects in standard CMOS inverter circuits.

A CAD assisted design and optimisation methodology for over-voltage ESD protection circuits

V.Vassilev^a,b, V.Vashchenko^c, Ph.Jansen^a, B.-J. Choi^c, A.Concannon^c, J.-J.Yang^c, G.Groeseneken^a,b, M.I.Natarajan^a, M.Terbeek^c, P. Hopper^c, M.Steyaert^b, H.E.Maes^a,b

IMEC, Kapeldreef 75, 3001 Leuven, Belgium
^b KUL, ESAT, Kasteelpark Arenberg 10, 3001 Leuven, Belgium
^c National Semiconductor Corp.,2900 Semiconductor Drive, Santa Clara, CA 95052-8090, USA

To reduce the cycle time and the cost of the design of ESD tolerant over-voltage I/O cells, a methodology for pre-silicon ESD protection optimisation is described, based on Technology Computer Aided Design (TCAD) (device level) and compact (circuit level) simulation studies. Using this methodology, first time right ESD tolerant over-voltage I/O cells were designed in a silicided 0.25 µm CMOS dual gate-oxide process. The methodology consists in a precise TCAD process calibration, a cascoded snapback NMOS compact model definition valid under ESD conditions, a model parameter extraction based on TCAD data and, finally, circuit level optimisation of the I/O protection circuits. Very good agreement was achieved between the simulated pre-silicon characteristics and the experimental behaviour of the I/O protection circuits.