Influence of the thermo-mechanical residual state on the power assembly modellization

Alexandrine Guédon-Gracia, Pascal Roux, Eric Woirgard, Christian Zardini
Laboratoire IXL CNRS UMR 5818, ENSEIRB, Université Bordeaux 1
351, cours de la Libération, 33405 Talence Cedex, FRANCE

During the assembly process of a power chip on its thermal dissipator, it appears a residual stress state, due to the difference between the thermal expansion coefficients of the assembly components: silicon, solder alloy, copper. The goal of this study is to show the influence of the residual stresses and strains on the solder joint thermal fatigue. Three numerical simulations of thermal cycles have been carried out by taking into account the residual stresses or not. A simple assembly model is used to reduce the simulation run time. For each case, the strain energy density accumulated in the solder joint is computed during each thermal cycle. The comparison of these values for each case shows that the residual stresses must be taken into account in the assembly lifetime study.

Study of influence of failure modes on lifetime distribution prediction of 1.55 µm DFB Laser diodes using weak drift of monitored parameters during ageing tests

L. Mendizabal¹, L. Bechou¹, Y. Deshayes¹, F. Verdier¹, Y. Danto¹, D. Laffitte², J.L. Goudard², F. Houé^2
1 IXL Laboratory, University Bordeaux 1-ENSEIRB-CNRS UMR 5818, 351 Cours de la Libération, 33405, TALENCE Cedex, FRANCE
² AVANEX-France, Route de Villejust, BP6, 91625 Nozay, FRANCE

High performances and high reliability are two of the most important goals driving the penetration of optical transmission into telecommunication systems ranging from 880 nm to 1550 nm. Lifetime prediction defined as the time at which a parameter reaches its maximum acceptable shift, remains the primary result in the estimation of reliability for a technology. In this paper, we demonstrate that bias current of well-mastered actual technologies of single mode 1.55µm Distributed Feedback (DFB) Laser diodes is still a relevant failure indicator to conclude on failure modes although very weak variations are measured (until 6%). Nevertheless, screening complementary parameters such as threshold current and optical efficiency close to operating conditions can assess more information about the failure mechanism. From experimental determination of failure law, statistic computations based on Monte-Carlo approach are detailed to calculate lifetime distributions for the different failure modes over 20 years in operating conditions. Finally, from cumulative failure functions, we highlight the strong interest to take into account of variations of complementary parameters allowing us to perform an improved determination of first times to failure in contrast with only bias current variations.

Comparative study of thermal cycling and thermal shocks tests on electronic components reliability

S. Moreau^a,b, T. Lequeu^a, R. Jérisian ^a
a LMP, 16 rue Pierre et Marie Curie, BP 7155, 37071 Tours cedex 2, France
^b STMicroelectronics, 16 rue Pierre et Marie Curie, BP 7155, 37071 Tours cedex 2, France

In this work, the first reliability results of Thermal Cycling Tests (TCT, air-air test) and Thermal Shock Tests (TST, liquid-liquid test) on medium power electronic components are discussed. The influence of dwell times, extremes temperatures and mean temperature is investigated. This study is based on statistical data correlated with information coming from failure analysis and confirmed by a basic FEM analysis.

Integrated thermo-mechanical design and qualification of wafer backend structures

G.Q. Zhang^a and J. Bisschop^b
a) Eindhoven University of Technology and Philips Centre for Industrial Technology, P.O. Box 218, 5600 MD, Eindhoven, The Netherlands, g.q.zhang@philips.com
b) Philips Semiconductors, P.O. Box 30008, 6534 AE, Nijmegen, The Netherlands

For Integrated Circuit (IC) wafer backend development, process developers have to design robust backend structures that guarantee both the functionality and reliability during waferfab processes, packaging, qualification tests and usage. Among many other possible failure modes, it is found that thermo-mechanical (thermal, mechanical and thermo-mechanical) related failures account for a large part of total failures of backend structures. Due to the rapid development of Cu/Low-k technologies and the inherited weakness of thermo-mechanical properties of Cu/Low-k stacks, thermo-mechanical reliability is becoming one of the major bottlenecks. The solutions of this problem relied on, among others, the development and implementation of innovative and integrated thermo-mechanical design and qualification methods. This paper summarises parts of our research results of developing methodologies, models and tools that can be used to design and qualify the wafer backend structures by integrating the design targets and requirements from both waferfab backend processes and packaging parameters.

Non destructive control of flip chip packages for space applications

M. Paillard ^a, C. Schaffauser ^a, C. Drevon ^a, J.L. Cazaux ^a H.R. Schubach ^b, F. Frese ^b
a Alcatel Space, 26 Avenue Champollion, BP1187, F-31037 Toulouse, France
^b Dantec Ettemeyer GmbH, Kaessbohrer Str. 18, D-89077 Ulm, Germany

Shrinking dimensions of flip chip assemblies make inspection of bumps or solder joints always more difficult as standard non destructive control techniques reach their resolution limits. This issue is particularly critical for RF flip chip assemblies manufactured at Alcatel Space with stud bumps as small as a few tens of micrometers regarding quality requirements from space industry. In this paper, non destructive control of flip chip packages is addressed by 3D-Electronic Speckles Pattern Interferometry (3D-ESPI). This original non contact and full field technique allows deformation measurements of microsystems with a sub-micron resolution and was successfully applied to detect defaults such as missing bumps in flip chip assemblies

Current crowding in faulty MOSFET: optical and electrical investigation

A. Tosi^a, F. Stellari^b, F. Zappa^a
a Politecnico di Milano, Dipartimento di Elettronica e Informazione
Piazza Leonardo da Vinci 32, 20133 Milano (Italy)
^b IBM T.J. Watson Research Center, Yorktown Heights - NY 10598 (USA)

In this paper we report an in-depth analysis of a current crowding phenomenon in a 0.55µm CMOS technology. Emission Microscopy (EMMI) technique was used to support the traditional electrical investigation for the interpretation of physical phenomena inside a MOS transistor. We identified a localized increase of the luminescence emission due to a local current crowding of the device under test. We ascribed the origins to a local higher electric field leading to an enhanced hot-carrier regime within the device. We carried out a detailed characterization by means of the joint use of photon emission analysis and electrical measurements.

Acoustic microscopy - a powerful tool to inspect microstructures of electronic devices

S.U. Fassbender and K. Kraemer
IFA (Institute for Acoustic Microscopy), Lerchenweg 16-18, 35729 Herborn, Germany
P.Czurratis, SAM TEC GmbH, P.O. 3111, 73641 Aalen

Due to the requirements of new semiconductor technologies and devices the structures of semiconductor chips are getting smaller and smaller and the layered constructions are getting more complex. The inspection of these small and thin structures leads to new demands on the NDT methods (non destructive testing), especially in lateral and depth resolution. X-ray tomography as one inspection method has limitations to detect special types of cracks and delaminations in general. New developments in Scanning Acoustic Microscopes (SAM) are able to detect cracks, delaminations, and other non homogeneities with improved image quality and resolution. Modern systems use frequencies between 3 MHz and 2000 MHz and are designed to detect defects even in the sub micron and nm range. In combination with new scanning units providing step sizes of less than 0.1 µm, new modified transducers and special software functions, new SAM`s inspect microelectronic devices fast, reliable and showing defect resolution and image contrast which have never been observed before.

Gallium Artefacts on FIB-milled Silicon Samples

Joachim C. Reiner, Philipp Nellen, Urs Sennhauser
EMPA - Electronics/Metrology Laboratory, Ueberlandstr. 129, CH-8600 Dübendorf, Switzerland

The Focused Ion Beam Machine (FIB) allows sample milling on the sub-micrometer scale by local sputtering. This is used to prepare sample cross sections for SEM investigation or TEM-transparent sample lamella. Here, for the case of silicon semiconductor sample preparation, two critical preparation artefacts are presented and analysed, both caused by re-deposition of material. In TEM images, sometimes dark, circular spots with diameters up to a few hundred nanometers are observed. Detailed analysis by SEM and TEM including EDX revealed gallium particles or droplets. A detailed investigation highlights the formation mechanism of this kind of re-deposition as well as of the closed-film type of re-deposition.

VCO phase noise improvement through direct passive component modification in the FIB

B. Domengès^a,1, B. Tiphaigne^b
a LAMIP, laboratoire de microélectronique ISMRA-Philips, Caen, France
^b STEPMIND OUEST, Parc d'Activités de la Folie Couvrechef (ACTIS 1), Caen, France

It is shown in this study that it is possible to decrease under a controlled way the resistance of a passive component through the deposition of a Pt strap parallely connected to the involved device polysilicon resistor. Each modification step being followed by an electrical characterization, the evolution of device VCO phase noise versus equivalent resistor value could be drawn and the optimum value quantified.

Failure analysis of vertical cavity surface emission laser diodes

F. Siegelin
Infineon Technologies AG, Failure Analysis, Balanstr. 73, 81343 Munich, Germany

Degradation of optical output is known as a major failing mode of oxide confined vertical surface emitting laser diodes (VCSEL). While in most cases these lasers show a rapid degradation, continuously reduced optical output by a wear out process is also possible. Failure analysis is essential for a detailed understanding of VCSEL fails. An analysis flow will be shown, comprising electrical and optical characterization as well as detailed transmission electron microscopy (TEM) inspection. Its usefulness will be demonstrated on the basis of case studies.

Failure analysis of RFIC Amplifiers

G. Mura^a, M. Vanzi^a, G. Micheletti^b
a Department of Electric and Electronic Engineering DIEE-INFM , University of Cagliari, Italy
^b Datalogic S.p.A, Bologna, Italy

This work investigates the physical mechanism, which leads to low and noisy signal (on board) of some RF amplifiers. In order to identify the failure mechanisms involved in these devices, a thorough failure analysis was planned. RF characterization, front and back etch inspection and SEM/EDS analysis concurred to explain the observed failure mode in terms of poor quality of the metal system.

Femtosecond Laser Ablation for Backside Silicon Thinning

F. Beaudoin^a, J. Lopez^b, M. Faucon^b, R. Desplats^a, P. Perdu^a
aCNES-THALES Laboratory, 18, Avenue Edouard Belin, 31401 Toulouse, France.
^bCELIA-PALA UMR 5107 Université Bordeaux 1-CNRS-CEA 351 cours de la libération 33405 Talence - France

Ultra-short pulse laser ablation has shown to be a promising technique for backside sample preparation [1]. It is contact-less, non-thermal, precise, repetitive and adapted to the various type of material present in IC packages. In this paper we present the application of ultra-short pulse laser ablation to silicon thinning. Special care is taken to minimize the silicon RMS roughness to less than 1µm with a controlled depth

A Novel Automatic Polishing Technique for Micro-Controllers with 450 off Si <100> Rotation

I. Grimberg^a*, H. Coulson^b, K. Williamson^b, J. Pohl ^b, Z. Shafrir^a, E. Raz^a
a Sagitta Ltd, 5 Hagavish St. P.O.B. 2047, Kfar Saba 44641, Israel
^b ATMEL, North Tyneside, Middle Engine Lane, Silverlink, Newcastle NE28 9NZ, United Kingdom

With scaling down of Integrated Circuits (IC) critical dimensions, the proportion of leakage current has increased drastically. ATMEL utilizes a novel technology based on 45° rotation relative to Si <100> (c-flat) for reducing channel leakage current in CMOS devices. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current was reduced by up to two orders of magnitude for a 0.21 µm N-channel CMOS device. The 45° rotation technology poses several challenges for traditional Failure Analysis (FA) methods like cleaving and polishing. The metal/polysilicon features no longer align with the cleave plane, requiring special cleaving at 45°. The sharp edge and the differential increase in the polished area cause difficulties in controlling the process manually. An innovative technique, developed by Sagitta, for cleaving and automatic polishing of rotated Si devices for FA and process control monitoring will be discussed in this paper.

AFM-based scanning capacitance techniques for deep sub-micron semiconductor failure analysis

Guenther Benstetter^a1, Peter Breitschopf^a, Werner Frammelsberger^a, Heiko Ranzinger^a, Peter Reislhuber^a, Thomas Schweinboeck^c
a University of Applied Sciences Deggendorf, Deggendorf, Germany,
^b University of the West of England, Bristol, United Kingdom
^c Infineon Technologies, Munich, Germany

In this study diffusion areas and junctions of semiconductor structures have been analyzed by Atomic Force Microscopy (AFM) - techniques such as Scanning Capacitance Microscopy (SCM), Scanning Capacitance Spectroscopy (SCS), High Speed Scanning Capacitance Spectroscopy (HSSCS) and Differential Scanning Capacitance Spectroscopy (DSCS). The experimental setups are explained and the measurement procedures are described. Beginning with basic sample preparation techniques, cases studies are presented and advantages and disadvantages of the different techniques are discussed

On the Use of Neural Networks to Solve the Reverse Modelling Problem for the Quantification of Dopant Profiles Extracted by Scanning Probe Microscopy Techniques

Mauro Ciappa^a, Maria Stangoni^a, and Wolfgang Fichtner^a Elisa Ricci^b and Andrea Scorzoni^b
a Swiss Federal Institute of Technology (ETH) Zurich, Integrated Systems Laboratory, Zurich, Switzerland
^b University of Perugia, Faculty of Engineering, Perugia, Italy

In this paper, we present the use of artificial neural networks to extract the doping profile from the one-dimensional carrier concentration distribution (and viceversa). The values of the weights and of the biases are computed for the optimum network configuration . The performances and the noise immunity characteristics of the proposed network are assessed and compared with those of the standard techniques.

Investigation of SEU sensitivity of Xilinx Virtex II FPGA by pulsed laser fault injections

R. Desplats^a, S. Petit^c, S. Rezgui^d, C. Carmichael^d, P. Fouillat^b, D. Lewis^b
aCNES- French Space Agency, 18, avenue Edouard Belin 31401 Toulouse - France
^bIXL Laboratory, 351 cours de la Libération, 33405 Talence Cedex - France
^cONERA, 2, avenue Edouard Belin, 31400 Toulouse - France
^dXilinx, Group HI-REL, Aerospace & Defense Products, Xilinx, 2100 Logic Drive, San Jose, CA

In critical applications, charged particles coming from outer space may locally ionize IC structures. In the case of a memory, a change from 0 to 1 (or 1 to 0) occurs. To investigate the reliability of RAM based FPGAs, a pulsed laser is used to change memory bits. Each change may affect programming of the device thus changing its function. In this document, we will present a unique methodology consisting in the injection of localized SEUs in Xilinx Virtex II FPGAs for an optimal evaluation of the sensitivity of input/output blocks as well as the power on reset (POR) circuitry to SEUs. This methodology is based on an innovative combination of existing techniques: Radiation beam, software and laser fault injections we will describe how each technique complements the others to evaluate sensitivity of integrated circuits.

Light Emission From Small Technologies. Are Silicon Based Detectors Reaching Their Limits?

M. Remmach^a, R. Desplats^a, P. Perdu^a, J. P. Roux ^b, M. Vallet ^b, S. Dudit ^c, P. Sardin^c , D. Lewis^d
a CNES- French Space Agency - 18 avenue Edouard BELIN - 31401 Toulouse Cedex 9 - France
^b NPTest Inc - 150 Baytech Drive- San Jose, CA 95134 - USA
^c ST Microelectronics - 850 rue Jean Monnet - 38926 Crolles cedex - France
^d IXL Laboratory, 351 cours de la Libération, 33405 Talence Cedex - France

After a brief review of light emission in field effect transistors, we extract some electrical and physical parameters linked to the emission of photons such as VDD and channel length. Using 120nm technology structures (nMOS, pMOS, inverters...) we compare emissions with the following detectors: CDD, MCT for static emission, PICA, SiAPD and SSPD for time resolved photon emission (TRE). Results are interpreted according to the quantum efficiency of detectors as a function of wavelength. Finally, the wavelength shift is addressed by confronting practical results with earlier publications on light emission spectra.

Field Failure Mechanism Investigation of GaAs based HBT Power Amplifier Module (PAM)

Jae-Seong Jeong*, Jong-Shin Ha, Sang-Deuk Park
Advanced Technology Group, CS Management Center, Samsung Electronics CO., LTD 416, Maetan-3Dong, Paldal-Gu, Suwon City, Gyeonggi-Do, Korea

In this paper, field failure analysis of GaAs based HBT Power Amplifier Module (PAM) for Wireless Handset was conducted by utilizing Photoemission Spectrum analyzer (PSA) and Real-time Electrical Stress Analysis (RTESA) method. And, by repeating the failures intentionally, we could have created a failure mechanism. In Case of field failure PAM, among the balanced amplifiers, damaged HBT finger array were turned-on at degraded voltage (Vref=1.4V) as compared to normal applied reference voltage (Vref=3.0V), and high current was observed at reference voltage control circuit. Failure level was measured with Electrostatic Discharge (ESD) test. As a result, Vcc2 (Supply voltage) common mode ESD (PD & ND-mode) level were at the lowest as 1.6kV (Class I, Ref. JESD22-A114-B). In addition, all degraded reference voltage, DC characteristics, and Steady-state photoemission profile after ESD damage presented the same result as field failure sample. Also, ESD damage roots defined with failure mechanism could have verified as real-time photoemission 2D profile. We acquired results that PD and ND mode damage root thought real-time photoemission profile were different. There are various failure factors to cause PAM lifetime degradation. With this analysis in the report, as a conclusion, we could have proved that damages caused by ESD are the main reason for PAM field failure. Especially ESD which is inserted to GND in Vcc2 common mode (PD & ND-mode) was the major factor of PAM reliability degradation.

Reliability study of Power RF LDMOS for Radar application

H. Maanane^a, P. Bertram^b, J. Marcon^a, M. Masmoudi^a, M. Belaid^a, K. Mourgues^a, P. Eudeline^b and K. Ketata^a
a LEMI, University of Rouen, IUT Rouen, 76821, Mont Saint Aignan, France
^b THALES Air Defence, ZI du Mont Jarret, 76520 Ymare, France

This paper presents an innovative bench specifically dedicated to high RF power device lifetime tests under pulse conditions for radar application. This bench is able to stress eight devices in order to have a statistic sample for MTTF estimation. The bench allows to apply and keep track of all RF powers, voltages and temperatures. Both electrical and thermal stresses applied should lead to modifications of the device performances. A commercial LDMOS transistor has been chosen for the first tests. This paper presents the electrothermal modelling performed to understand the degradation phenomenons that appear during device ageing. The model will be used as a reliability tool in order to correlate RF LDMOS electrical parameters with any kind of degradation phenomenon.

Experimental characterization of temperature distribution on Power MOS devices during Unclamped Inductive Switching

E. D'Arcangelo, A. Irace, G. Breglio and P. Spirito
Dipartimento di Ingegneria Elettronica e delle Telecomunicazioni, Università degli Studi di Napoli "Federico II" Via Claudio, 21 I-80125 Naples, ITALY

In this paper we present experimental results of dynamic thermal mapping for the characterization of electro-thermal behaviour of new power MOSFET devices during Unclamped Inductive Switching. Based on a suitable electrical driving circuit and on a direct radiometric detection of the device temperature, the proposed system is able to acquire the temperature map over the dye area with high spatial (less than 10(m) and time (less than 2µs) resolution, and good temperature (less than 1°C) resolution. This capabilities are confirmed by the results reported in the paper, where two different low voltage (less than 60V) low on-resistance (less than 10mΩ) multi-cellular power MOSFETs devices have been tested. Uneven temperature distributions due to differences in dye size and dissipated power have been detected during the UIS transient.

Comparison Between the Behaviour of Punch-Through and Non-Punch-Through Insulated Gate Bipolar Transistors Under High Temperature Reverse Bias Stress

C. O. Maiga, H. Toutah, B. Tala-Ighil, B. Boudart,
Site Universitaire, LUSAC, BP78, 50130 Cherbourg-Octeville, France.

The aim of this work is a comparative study of the High Temperature Reverse Bias (HTRB) stress effects on the Punch-Through (PT) and Non-Punch-Through (NPT) Insulated Gate Bipolar Transistors. The technological difference between these transistors is the N+ buffer layer, which is only built in the PT structure. These two different structures of IGB transistors have practically the same electric parameters: V_CEmax=600V; I_CEmax = 16A for the PT-IGBT and V_CEmax=600V; I_CEmax = 16A for the NPT one at 25°C. The electric stress has been achieved during 1200 hours at 140°C with 0.8V_CEmax Collector - Emitter bias. The obtained results show the variation of the threshold voltage, the on-state voltage drop and switching parameters under HTRB stress effect. So, some interesting information concerning the ageing of these two types of IGBT under this stress effect have been highlighted.

Passivation schemes to improve power devices HAST robustness

L. Allirand^a, B. Regairaz^b
a T&M organization ,Technology Solutions, FREESCALE SAS, 134 avenue du Général Eisenhower. BP72329 31023 Toulouse. Cedex 1. FRANCE
^b T&M organization, Die Manufacturing MOS20, FREESCALE SAS, 134 avenue du Général Eisenhower. BP72329 31023 Toulouse. Cedex 1. FRANCE

Threshold voltage shifts observed on MOSFETs Power Devices after HAST have been correlated to the presence of a Nitride / Oxide passivation layer. Investigations of standard passivation schemes: PECVD USG / TEOS / Nitride and Polyimide have led us to the conclusion that the classical "Si-H bonds" model was not 100% satisfactory to explain our failure mode. Therefore other aspects such as: mechanical constraints, Si-H bonds concentration effect have been studied. As a result, process integration guidelines for improving MOSFETs Power devices HAST robustness are presented.

Enhancement of breakdown voltage for Ni-SiC Schottky diodes utilizing field plate edge termination

T. Ayalew y, A. Gehring , T. Grassery, and S. Selberherr
Christian-Doppler-Laboratory for TCAD in Microelectronics at the Institute for Microelectronics
Institute for Microelectronics, TU Vienna, Gußhausstraße 27-29, A-1040 Wien, Austria

In this work the improvement in breakdown voltage of Ni-SiC Schottky diodes utilizing field plate edge termination is presented. We have performed numerical investigations on how the addition of the field plate affects the relationship between the device structure, performance, and reliability. The key parameters that alter the overall device performance have been optimized using the device simulator MINIMOS-NT. This structure with a high barrier height metal such as Ni results in Schottky diodes with breakdown voltages in excess of 35% compared to the Schottky diodes without edge termination. The ratio of the maximum field under the anode corner to the field under the center of the contact at the same depth is reduced by a factor of two for edge terminated diodes for a wide range of doping levels. The leakage current in reverse biased operation is lowered by two orders of magnitude at room temperature and nearly by an order of magnitude at 500 K.

Compare of SOI and SOS LIGBT structure for the thermal conductivity and self-heating characteristics

J. Y. Kim^a, S. W. Park^a, M. C. Jung^a, C. H. Kim^a, M. Y. Sung^a, D. H. Rhie ^b E. G. Kang^c, N. G. Kim^d, S. C. Kim^d
a Department of Electrical Engineering, Korea Univ, 1, 5ka, Anam-dong, Sungbuk-ku, Seoul, Korea
^b Department of Electrical Engineering, Suwon Univ., Bongdam-eup, Hwaseong-si, Gyeonggi-do,Korea
^c Department of Electronic Enginnering, Far East Univ., Gamgok-myun, Uemsung-gun, Chung-buk, Korea
^d Korea Electrotechnology Search Institute, Chang-won, Korea

The electrothermal simulation of high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) in thin Silicon on insulator (SOI) and Silicon on sapphire (SOS) for thermal conductivity and sink is performed by means of MEDICI. The finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on-insulator (SOI) devices. In this paper, using for SOI LIGBT, we simulated electrothermal for device that insulator layer with SiO₂ and Al₂O₃ at before and after latch up to measured the thermal conductivity and temperature distribution of whole device and verified that SOI LIGBT with Al₂O₃ insulator had good thermal conductivity and reliability.

Analysis of wire bond and metallization degradation mechanisms in DMOS power transistors stressed under thermal overload conditions

Th. Detzel, M. Glavanovics, K. Weber
Infineon Technologies Austria AG, Siemensstrasse 2, A-9500 Villach

This paper reports about investigations concerning the degradation of the power metallization and wire bonds of smart power devices repeatedly stressed under cyclic thermal overload conditions. The fatigue of the interface between power metallization and bond wire finally leads to device failure (Drain-Source short circuit or open). Evaluation of experimental data revealed that for life time prediction a "modified Coffin-Manson Equation" describing time to failure as a function of thermal as well as electrical stress parameters is applicable. Electrical and physical analysis of stressed devices is presented. Possible failure mechanisms of the DMOS silicon device are discussed.

A new approach to the modeling of oxide breakdown on CMOS circuits

R. Fernández, R. Rodríguez, M. Nafría, X. Aymerich
Departament d'Enginyeria Electrònica, Universitat Autònoma de Barcelona, 08193, Bellaterra, Barcelona, Spain

The influence of the oxide breakdown (BD) hardness and location on the performance of several CMOS circuits has been simulated. A simple MOSFET transistor model which takes into account the oxide BD has been used to do the analysis. The results show that the hardness of the BD could play an important role in determining the correct performance of the circuit and under certain conditions the circuits can still be functional.

Standard and C-AFM tests to study the post-BD gate oxide conduction of MOS devices after current limited stresses.

M. Porti*, S. Meli, M. Nafría, X. Aymerich
Dept. Enginyeria Electrònica, Universitat Autònoma de Barcelona, 08193 Bellaterra, Spain

In this work, we have combined standard electrical tests with C-AFM experiments on SiO₂ gate oxides to investigate the influence of the nanometer scale conduction parameters (in particular, the area affected by the breakdown event, SBD), to the overall oxide post-BD conduction, IBD, measured on microelectronic sized devices for a wide range of current limits. Although a relation between both parameters can be established, the results show that the total current flowing through the BD spot is mainly determined by the conductivity at the oxide position where it is initially triggered.

Time dependent dielectric breakdown in a low-k interlevel dielectric

J.R. Lloyd, E. Liniger , S.T. Chen^a
IBM T.J. Watson Research Center, Yorktown Heights NY 10598, USA
^a IBM Microelectronics, Hopewell Jct. NY 1253, USA

Intralevel Time Dependent Dielectric Breakdown (TDDB) was studied in interdigitated comb structures comprised of standard Cu metallization and a low-k interlevel dielectric. The failure distribution was found to be best represented as being lognormal with sigma increasing as the field decreased. Kinetic studies revealed an exponential dependence on the electric field that fits 1/E closer than -E, but is not compelling in either case. The data fits a simple impact damage model

On the defects introduced by AC and DC hot carrier stress in SOI PD MOSFETs

M.Exarchos^a, F.Dieudonne^b, J.Jomaah^b, G.J.Papaioannou^a and F.Balestra^b
a University of Athens, Physics Dept., Solid State Physics Section, Panepistimioupolis, Athens 15784, Greece
^b IMEP (UMR CNRS/INPG/UJF), ENSERG BP 257, 38016 Grenoble Cedex 1, France

The defects introduced by hot carrier stress during on-state operation (DC stress) and dynamic operation (AC stress), of Unibond SOI MOSFETs (0.25µm gate length), are investigated. These defects are monitored by means of Deep Level Transient Spectroscopy (DLTS) technique, which is based on drain current transient signal recording. DLTS spectra of devices subjected to hot carrier stress revealed the presence of traps, some of which were previously reported in literature. Transient effects such as overshoot/undershoot, presented at DLTS spectra of partially depleted SOI devices, was overcome by using body contacted devices. The latter were studied further in order to monitor the body potential transients and to emerge information about the body excess charge recombination paths.

Reduced Hot Carrier Effects in Self-Aligned Ground-Plane FDSOI MOSFET's

Se Re Na Yun^a, Chong Gun Yu^a, Seok Hee Jeon^a, Chung Kyue Kim^b, Jong Tae Park^a,*, and Jean Pierre Colinge^c
a Department of Electronics Engineering, University of Incheon
^b Department of Computer Engineering, University of Incheon
#177 Dohwa-dong Namgu, Inchon, 402-749, Korea
^c Department of Electrical and Computer Engineering, University of California, Davis, 95616, USA

This paper reports the hot-carrier induced device degradation of fully depleted (FD) n-channel SOI MOSFETs with a self-aligned ground-plane electrode in the silicon substrate underneath the buried oxide. The ground-plane configuration is shown to reduce short-channel effects, BJT effects and hot-carrier effects. Based on measurements of hot-carrier degradation rate, it is predicted that the maximum allowable supply voltage of ground-plane FDSOI MOSFET is higher than that of FDSOI device without a ground plane

A new structure to monitor electrical transients during programming of EEPROM memory cells

N. Baboux^a, C. Plossu^a, P. Boivin^b
a Laboratoire de Physique de la Matière, UMR CNRS 5511, INSA de Lyon, B‚t. Blaise Pascal, 7 Av. Jean Capelle, 69621 Villeurbanne, France
^b STMicroelectronics, ZI Rousset, BP2, 13106 Rousset Cedex, France

In this paper, we present an original test structure, representative of a FLOTOX (FLOating gate Thin OXide) EEPROM technology, that allows to monitor both the programming current (by direct measurement) and the floating gate potential (indirectly by the so-called "floating gate technique") during write and erase operations. Experimental electrical transients are compared to simulations based on a simplified electrical model. It is then shown that these procedures can be powerfully applied to the study of endurance of EEPROM devices and of the evolution of their programming window with operating temperature.

Evaluation of STI degradation using temperature dependence of leakage current in parasitic STI MOSFET

Oleg Semenov^a , Michael Obrecht^b and Manoj Sachdev^a
a Dept. of Electrical and Computer Engineering, University of Waterloo, Waterloo, Canada N2L 3G1
^b Siborg Systems Inc., 24 Combermere Crescent, Waterloo, Ontario, Canada N2L 5B1

Shallow trench isolation (STI) has become the most promising isolation scheme for ULSI applications. However, the trench isolation suffers from dislocations and oxidation induced stacking faults. Such faults are typically located near trench edges. These STI faults increase the junction leakage current and may turn-on the parasitic STI MOSFET resulting in significant leakage current through the trench isolation. In this paper we analyze the mechanism of parasitic STI MOSFET formation and investigate the temperature dependence of its leakage current. Simulation results show that the value of drain current of parasitic STI MOSFET can be used for evaluation of STI degradation. The abnormal temperature dependence of the parasitic drain current with floating body can be used as a faulty STI indicator.

Reliability determination of aluminium electrolytic capacitors by the mean of various methods. Application to the protection system of the LHC

F. Perisse^a, P. Venet^b, G. Rojat^b
a LEA Boulevard Marie & Pierre CURIE - Teleport 2 BP 30179, F86962 Futuroscope, France
^b CEGELY UCB Lyon 1, Bat Omega,Domaine universitaire de la Doua 69622 Villeurbanne, France

The lifetime of power electronic components is often calculated from reliability reports, but this method can be discussed. We compare in this article the results of various reliability reports to an accelerated ageing test of component and introduced the load-strength concept. Large aluminium electrolytic capacitors are taken here in example in the context of the protection system of LHC (Large Hadron Collider) in CERN where the level of reliability is essential. We notice important differences of MTBF (Mean Time Between Failure) according to the reliability report used. Accelerating ageing tests carried out prove that a Weibull law is more adapted to determinate failure rates of components. The load-strength concept associated with accelerated ageing tests can be a solution to determine the lifetime of power electronic components.

Failure Analysis of RuO₂ Thick Film Chip Resistors

S.Podda^a, G.Cassanelli^b, F.Fantini^b, M.Vanzi^a
a Department of Electronic Engineering, University of Cagliari-INFM Piazza D'Armi 09123Cagliari,Italy
^b University of Modena e Reggio Emilia Dipartimento di Ingegneria dell'Informazione, Modena Italy

This work presents the results of Failure Analysis carried out on RuO₂ Thick Film Chip Resistors in field failed. Microscopical investigation performed on virgin, degraded and open circuit devices showed the failure mechanism involved: evidence for mechanical cracks may be related with the observed degradation and failures. On the failed and degraded devices some bad adhesion of the resistive film on the metallized alumina has been observed, which also could be consistent with thermomechanical hypothesis for the failure mechanism

First step in the reliability assessment of ultracapacitors used as power source in hybrid electric vehicles

W. Lajnef, J.M. Vinassa, S. Azzopardi, O. Briat, C. Zardini
Laboratoire IXL CNRS UMR 5818 -FR 2648 -Univ. Bordeaux 1, Talence France

Regarding the new power requirements in hybrid electric vehicles, ultracapacitors seem to be very attractive. The examination of their existing characteristics, combined with the pulsed charge-discharge current mode, leads us to propose an original approach for electro-thermal characterization of ultracapacitors. Therefore, a dedicated test bench has been designed allowing both electric and thermal behaviour investigations. The principle of this study is to investigate the ultracapacitors thermal behaviour thanks to several specific cyclic current profiles. The use of these profiles will constitute the very first step in an assessment of the ultracapacitors reliability devoted to power source operation in automotive applications.

Study and validation of a power-rail ESD clamp in BiCMOS process with a reduced temperature dependency of its leakage current

F. Barbier ^a,e, F. Blanc ^a, A. Le Grontec ^a, R. Colclaser ^b, T. Smedes ^c M. Johnson ^d, S. Bardy ^a, P. Descamps ^e
a Philips Semiconductors Caen, 2 rue de la girafe, France
^b Philips Semiconductors Fishkill,12533-1279 Hopewell junction, NY, USA
^c Philips Semiconductors Nijmegen, Gerstweg 2, The Netherlands
^d Philips Semiconductors San Jose, 1101 Mc Kay Dr, CA, USA
^e LaMIP, Laboratoire de Microélectronique ENSI Caen-Philips, 2 rue de la girafe, France

In this paper, we present a study, development and qualification of an improved power-rail ESD clamp (called "RC-PSC") in a 40 GHz BiCMOS process. The leakage of the previous version of the clamp (called "6d-PSC") showed a strong dependence on temperature, resulting in failures during HTOL (High Temperature Operational Life) and latchup testing. At 150°C and supplied at 3.3V, the leakage current has been successfully reduced from 40 µA to 30 nA, without a degradation of ESD robustness.

The Failure Analysis of High Voltage Tolerance IO Buffer under ESD

Tao Cheng, Y.S. Shyu
Media Tek Inc., No. 1-2, Innovation Road 1 Science-Based Industrial Park, Hsin-Chu City, Taiwan 300, R.O.C.

The failure analysis of high voltage tolerance (HVT) IO buffer is studied in this report. Different layout considerations and dummy device arrangement are studied to explain the impact of ESD current flow uniformity on the top gate of HVT IO buffers. Better ESD performance is come from uniform current flow by matched gate-connecting resistance and matched top gate loading. It is performed by appropriate metal routing and suitable dummy device arrangement. The ESD current uniformity is dominated by top gate voltage of HVT IO buffers from our study. The IC samples were fabricated in a 0.18µm CMOS with CoSi salicide 1P6M process. The failure mode is notched drain/poly edge damage. It is analyzed by OBIRCH(Optical Beam Induced Resistance Change), SEM, and TEM.

Study of the ESD defects impact on ICs reliability

F. Essely^a, C. Bestory^c, N. Guitard^b, M. Bafleur ^b, A. Wislez ^c, E. Doche ^c, P. Perdu^d, A. Touboul^a, D. Lewis^a,
^a IXL Laboratory, ENSEIRB, Université Bordeaux 1, 351, Cours de la Libération, 33405 Talence, France
^b LAAS-CNRS, avenue Edouard Belin, 31401 Toulouse, France
^c LCIE, avenue Edouard Belin, 31401 Toulouse, France
^d CNES-Thales laboratory - Bpi 141418, avenue Edouard Belin, 31401 Toulouse, France

This paper deals with a study on multiple electrostatic discharge (ESD) on integrated circuits (IC). Standards help define a susceptibility threshold of an IC to a single ESD zap. But during the lifetime of an IC, it will be stressed by multiple discharges. After electrical characterisation, series of low-level ESD stresses were applied to two commercially available integrated circuits using the human body model and the charged device model. It is shown that cumulative ESD stresses, even at a level below the failure one, significantly impact the IC lifetime by creating latent defects. In the next step, we localize the defect in failed devices with non destructive characterisation techniques such as EMMI, OBIRCH and OBIC to get a better understanding of the ESD phenomenon.

The Impact of CMOS technology scaling on MOSFETs second breakdown: Evaluation of ESD robustness

O. Semenov^a, H. Sarbishaei a, V. Axelrad b and M. Sachdev^a
a Dept. of Electrical and Computer Engineering, University of Waterloo, Waterloo, Canada N2L 3G1
^b Sequoia Design Systems, 137 Chapman Rd., Woodside, CA, USA 94062

The impact of CMOS technology scaling on the second breakdown of ESD protection devices has been investigated using 2-D simulations and analytical calculations. It is shown that the second breakdown trigger current (It₂) can not be reliably used as an ESD robustness criterion in sub-0.18 um ESD protection devices. When a technology feature size is reduced, the doping of drain and drain extension regions is significantly increased. Thus, the ESD device failure due to the self-heating effect occurs without the second snapback region in high current I-V curve and It₂ current can not be properly extracted. Instead of It₂ current criterion, we propose to use the maximum failure temperature criterion.

A case study of ESD failures at random levels: analysis, explanation and solution

T. Wu ^a,b, T. Smedes ^b, J.P. Lokker ^b, S-N. Mei ^c, J.W. Slotboom ^a
a Delft University of Technology, Mekelweg 4, 2628 CD Delft, the Netherlands
^b Philips Semiconductors, Gerstweg 2, 6534 AE Nijmegen, the Netherlands
^c Philips Semiconductors, Fishkill, 2070 Route 52, Hopewell Junction, NY, USA

A product exhibiting fails at random ESD levels is extensively investigated by a combination of experiments and simulation. It is shown that the cause of the failure is too stringent lithography settings for one of the process steps. Solutions by process optimisation and design improvements are discussed. After applying these the 4 kV specification level is easily met

A study of an abnormal ESD failure mechanism and threshold voltage caused by ESD current zapping sequence

Yong-Ha Song, Choong-Kyun Kim, Moo-Young Park, Bum-Suk Kye Jeong-Il Seo, Dong-Soo Cho, Taek-Soo Kim, Gab-Soo Han
System LSI Division, Semiconductor Business, SAMSUNG Electronics Co. Ltd., ASIC Development Team, ASIC Design 1 P/T
San #24, Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyunggi-Do, Korea

This paper presents a proposal on ESD (Electro Static Discharge) test method to understand an abnormal ESD failure caused by ESD current zapping sequence and to define an exact ESD threshold voltage. The abnormal ESD failure and threshold voltage level can not be detected by the prevailing used ESD test method which zapping ESD current stress to pins of DUT (Device Under Test) sequentially and automatically. Therefore this paper will show the abnormal ESD failure mechanism and also how to detect the actual ESD threshold voltage properly.