Article : [PAP287]

Titre : J.H. STATHIS, D.J. DiMARIA, Reliability projection for ultra-thin oxides at low voltage, IEDM'98, pp. 167-170.

Cité dans : [CONF033] IEDM, IEEE International Electron Devices Meeting, juin 2002.
Cité dans :[PAP285]

Stockage : Thierry LEQUEU
Lien : private/STATHIS1.pdf - 325 Ko, 4 pages.
Lien : PAP285.HTM#Bibliographie - référence [2].
Source : Electron Devices Meeting, 1998. IEDM '98 Technical Digest., International
Pages : 167 - 170
Date : 6-9 Dec. 1998
ISBN : 0-7803-4774-9
Info : IEEE Catalog Number: 98CH36217

Info : Total Pages : 1080
References : 15
Accession_Number : 6182499

Abstract :
The rate of defect generation by electrical stress in silicon
dioxide has been measured as a function of gate voltage down to 2
V on a variety of MOSFETs with thickness in the range 1.4-5 nm.
The critical defect density necessary for destructive breakdown
has also been measured in this thickness range. These quantities
are used to predict time to breakdown for ultra thin oxides at
low voltages. The properties of the breakdown distribution, which
becomes broader as the oxide thickness is reduced, are used to
provide reliability projections for the total gate area on a
chip. It is predicted that oxide reliability may limit oxide
scaling to about 2.6 nm (CV extrapolated thickness) or 2.2 nm (QM
thickness) for a 1 V supply voltage at room temperature and that
the current SIA roadmap will be unattainable for reliability
reasons by sometime early next century.

Subject_terms :
integrated circuit reliability; reliability projection;
ultra-thin oxides; defect generation; electrical stress; gate
voltage; MOSFETs; critical defect density; destructive breakdown;
time to breakdown; reliability projections; total gate area;
oxide reliability; oxide scaling; SIA roadmap; 2 V; 1.4 to 5 nm;
1 V

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