"PACKAGE THERMAL RESISTANCE MODEL DEPENDENCY ON EQUIPMENT DESIGN", 1988.

"PACKAGE THERMAL RESISTANCE MODEL DEPENDENCY ON EQUIPMENT DESIGN", 1988. Copyright - [Précédente] [Première page] [Suivante] - Home

Article : [ART579]

Info : REPONSE 26, le 13/07/2004.

Titre : PACKAGE THERMAL RESISTANCE MODEL DEPENDENCY ON EQUIPMENT DESIGN, 1988.

Cité dans : [DIV442]  Recherche sur les mots clés THERMAL RESISTANCE, juillet 2004.

Auteur : Andrews, James A. (Motorola SPS, Phoenix, AZ, USA)

Meeting : Fourth Annual IEEE Semiconductor Thermal and Temperature Measurement Symposium, Proceedings 1988.

Info : organization : IEEE, Components, Hybrids, & Manufacturing Technology Soc, New York, NY, USA
Location : San Diego, CA, USA
Date : 10 Feb 1988-12 Feb 1988

Source : Publ by IEEE, New York, NY, USA.Available from IEEE Service Cent (cat n 88CH2530-4), Piscataway, NJ, USA p 122-129
Année : 1988
Meeting_Number : 11491
Document_Type : Conference Article
Language : English
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Abstract :
A physical model is presented that describes mechanisms for operating-equipment junction-to-ambient thermal resistance in excess of a typical component manufacturers' data-sheet value by as much as a factor of four under constant cooling conditions.The model accounts for the discrepancy between system thermal performance of a package and data-sheet thermal resistance value which are not accompanied by qualifying data in the form of junction-to-header thermal resistance, board temperature rise over ambient, convection coefficient, mounting sensitivity, and power dissipation.The eight constants used to predict inherent increases in package thermal resistance when going from the data-sheet-specified operating conditions to the excess-value conditions are described.These constants and procedures for obtaining them are given for dual in-line packages (DIPs), pin-grid arrays (PGAs), small-outline transistors (SOTs), and plastic leaded chip carriers (PLCCs).

Références : 12 refs.

Accession_Number : 1988(9):134233 COMPENDEX

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