SHENAI K., HENNESSY W., CHEZZO M., "A novel trench planarization technique using polysilicon refill, polysilicon oxidation, and oxide etchback", ISPSD'91.

SHENAI K., HENNESSY W., CHEZZO M., "A novel trench planarization technique using polysilicon refill, polysilicon oxidation, and oxide etchback", ISPSD'91. Copyright - [Précédente] [Première page] [Suivante] - Home

Article : [99ART109]

Titre : SHENAI K., HENNESSY W., CHEZZO M., A novel trench planarization technique using polysilicon refill, polysilicon oxidation, and oxide etchback, ISPSD'91.

Cité dans : [CONF007] ISPSD, Internationnal Symposium on Power Semiconductor Devices & Integrated Circuits
Cité dans : [DIV137]  Recherche sur les mots clés : FIABILIT* ou RELIABILITY, octobre 1999.
Cité dans : [DATA041] Conférence ISPSD'91, Third Internationnal Symposium on Power Semiconductor Devices & ICs, Baltimore MD, April 22-24 1991.
Cité dans : [DIV293]  Recherche sur l'auteur Krishna SHENAI, mars 2004.

Auteur : Shenai, K.
Auteur : Hennessy, W.
Auteur : Ghezzo, M.
Editors : Shibib, M.A., Baliga, B.J. General Electric Corp. Res. & Dev., Schenectady, NY, USA

Appears : Power Semiconductor Devices and ICs, 1991. ISPSD '91., Proceedings of the 3rd International Symposium on
Page : 198
Date : 22-24 April 1991
ISBN : 0-7803-0009-2, Total Pages: viii+260, Accession Number : 4155063
Stockage : Thierry LEQUEU
Lien : private/SHENAI.pdf - 1 page, 67 Ko.

Abstract :
Summary form only given. A trench planarization technique is
reported which uses polysilicon refill and sequential polysilicon
oxidation and oxide etchback processes. Silicon trenches with
varying trench depths (1-10 mu m) and trench aspect ratios were
successfully planarized using this technique. The process
uniformity across 4 in. dia. silicon wafers was excellent with
MOS gate yields in excess of 95%. Trench capacitors were
fabricated and tested for MOS gate interface characteristics and
reliability. Trench power MOSFETs were fabricated using a
conventional two-step RIE (reactive ion etching) process as well
as the proposed technique. It was found that the proposed
technique resulted in significant improvements in gate yield and
process uniformity, and is easily adaptable in a manufacturing
environment for fabricating high-density trench-based active
devices, isolation structures, and interconnections.<>

Subjet_terms :
trench planarization technique; polysilicon refill; polysilicon
oxidation; oxide etchback; trench depths; trench aspect ratios;
process uniformity; MOS gate yields; gate interface
characteristics; reliability; power MOSFETs; RIE; gate yield;
process uniformity; isolation structures; interconnections; 1 to
10 micron; insulated gate field effect transistors; oxidation;
power transistors; sputter etching

Reference_cited : 2

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