Revue : [REVUE465]

Titre : Elsevier Science, Microelectronics Reliability, Volume 44, Issue 1, Pages 1-182, January 2004.

Cité dans : [DATA197] Les revues Microelectronics Reliability et Microelectronics Journal, ELSEVIER, décembre 2004.

Volume : 44
Issue : 1
Pages : 1-182
Date : January 2004

[1] : Electron transport through broken down ultra-thin SiO2 layers in MOS devices, Pages 1-23
Enrique Miranda and Jordi Suñé
Lien : vide.pdf - | Full Text + Links | PDF (598 K)

[2] : Influence of mobility model on extraction of stress dependent source–drain series resistance, Pages 25-32
M. M. De Souza, S. K. Manhas, D. Chandra Sekhar, A. S. Oates and P. Chaparala
Lien : vide.pdf - | Full Text + Links | PDF (426 K)

[3] : A review of electrostatic discharge (ESD) in advanced semiconductor technology, Pages 33-46
Steven H. Voldman
Lien : vide.pdf - | Full Text + Links | PDF (639 K)

[4] : Effects of electrical stress on mid-gap interface trap density and capture
cross sections in n-MOSFETs characterized by pulsed interface probing
measurements, Pages 47-51
Hyuck In Kwon, In Man Kang, Byung-Gook Park, Jong Duk Lee, Sang Sik Park,
Jung Chak Ahn and Yong Hee Lee
Lien : vide.pdf - | Full Text + Links | PDF (275 K)

[5] : Simulation of partially and near fully depleted SOI MOSFET devices and
circuits using SPICE compatible physical subcircuit model, Pages 53-63
Mohamed A. Imam, Mohamed A. Osman and Ashraf A. Osman
Lien : vide.pdf - | Full Text + Links | PDF (428 K)

[6] : Hole injection enhanced hot-carrier degradation in PMOSFETs used for
systems on chip applications with 6.5–2 nm thick gate-oxides*1, Pages
65-77
A. Bravaix, D. Goguenheim, N. Revil and E. Vincent
Lien : vide.pdf - | Full Text + Links | PDF (466 K)

[7] : New distributed model of NPT IGBT dedicated to power circuits design,
Pages : 79-88
G. Bonnet, P. Austin and J. L. Sanchez
Lien : vide.pdf - | Full Text + Links | PDF (509 K)

[8] : Origin of 1/f noise in lateral PNP bipolar transistors, Pages 89-94
Enhai Zhao, Zeynep Çelik-Butler, Frank Thiel and Ranadeep Dutta
Lien : vide.pdf - | Full Text + Links | PDF (332 K)

[9] : Applications of temperature phase measurements to IC testing, Pages 95-103
J. Altet, J. M. Rampnoux, J. C. Batsale, S. Dilhaire, A. Rubio, W. Claeys
and S. Grauby
Lien : vide.pdf - | Full Text + Links | PDF (693 K)

[10] : Integrated vapor pressure, hygroswelling, and thermo-mechanical stress
modeling of QFN package during reflow with interfacial fracture mechanics
analysis, Pages 105-114
Tong Yan Tee and Zhaowei Zhong
Lien : vide.pdf - | Full Text + Links | PDF (448 K)

[11] : The effect of model building on the accuracy of fatigue life predictions
in electronic packages, Pages 115-127
P. Towashiraporn, G. Subbarayan, B. McIlvanie, B. C. Hunter, D. Love and
B. Sullivan
Lien : vide.pdf - | Full Text + Links | PDF (791 K)

[12] : Thermal distribution calculations for block level placement in embedded
systems, Pages 129-134
Rajendra M. Patrikar, K. Murali and Li Er Ping
Lien : vide.pdf - | Full Text + Links | PDF (365 K)

[13] : Chip on paper technology utilizing anisotropically conductive adhesive for
smart label applications, Pages 135-140
Jad S. Rasul
Lien : vide.pdf - | Full Text + Links | PDF (494 K)

[14] : Design and simulation of micromechanical thermal converter for RF power
sensor microsystem, Pages 141-148
Jiri Jakovenko, Miroslav Husak and Tibor Lalinsky
Lien : vide.pdf - | Full Text + Links | PDF (532 K)

[15] : Thermosonic flip-chip bonding for SAW filter, Pages 149-154
Taizo Tomioka, Tomohiro Iguchi and Ikuo Mori
Lien : vide.pdf - | Full Text + Links | PDF (409 K)

[16] : Flip-chip packaging solution for CMOS image sensor device, Pages 155-161
Jong-heon Kim, In-Soo Kang, Chi-jung Song, Young-Jik Hur, Hak-Nam Kim, Esdy Baek and Tae-Jun Seo
Lien : vide.pdf - | Full Text + Links | PDF (592 K)

[17] : Single-equation model for low and high voltage soft breakdown conduction, Pages 163-166
E. Miranda and E. Mallaina
Lien : vide.pdf - | Full Text + Links | PDF (280 K)

[18] : Fatigue analysis of high-speed photodiode submodule by using FEM, Pages 167-171
K. S. Kim, H. I. Kim, C. H. Yu and E. G. Chang
Lien : vide.pdf - | Full Text + Links | PDF (393 K)

[19] : Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits, Pages 173-178
Mile K. Stojev, Goran Lj. Djordjevi and Tatjana R. Stankovi
Lien : vide.pdf - | Full Text + Links | PDF (256 K)

[20] : System on chip design languages; Anne Mignotte, Eugenio Villar, Lynn Horobin, editors, Kluwer Academic Publishers, Boston, 2002. Hardcover, pp. 283, plus IX, 141 €. ISBN 1-4020-7046-2, Page 179
Mile Stojcev
Lien : vide.pdf - | Full Text + Links | PDF (197 K)

[21] : Design criteria for low distortion in feedback OPAMP circuits; Bjornar Hernes, Trond Saether, Kluwer Academic Publishers, Boston, 2003. Hardcover, pp. 160, plus XXV, 110 €. ISBN 1-4020-7356-9, Pages 181-182
Mile Stojcev
Lien : vide.pdf - | Full Text + Links | PDF (199 K)

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