Article : [ART157]

Info : REPONSE 5, le 04/02/2002.

Titre : A partitioning algorithm for technology-mapped designs on single-chip emulation systems.

Cité dans : [DIV313]  Recherche sur l'auteur Narayanaswani RANGANATHAN, février 2002.

Source : IEEE Transactions on Very Large Scale Integration (VLSI) Systems v 9 n 2 April 2001 2001.p 407-410
CODEN : IEVSE9
ISSN : 1063-8210
Année : 2001
Document_Type : Journal
Treatment_Code : Theoretical; Experimental
Language : English
Stockage :

Abstract :
Reconfigurable single-chip emulation systems were proposed as an alternative to multichip emulation
systems. Because they cannot be emulated on a single chip at once, large designs are sliced into partitions that
are downloaded and executed sequentially on the same reconfigurable emulation chip. In this paper, we
address the problem of partitioning a design on a reconfigurable single-chip emulator under resource
constraints. First, we extract an acyclic flow graph of the design to be emulated. Then, we model the problem
as an integer linear programming problem (IP) based on the acyclic flow graph of the design where the
structure of the assignment and precedence constraints produce a tight formulation. To partition a design, our
algorithm uses two distinct steps with different objectives. In the first step, we minimize the number of cycles
needed to schedule every look-up table (LUT) in the circuit. Then flip-flops (FFs) are inserted into the
appropriate cycles of the schedule in the second step. Experiments are conducted on small- and medium-size
circuits from the MCNC Partitiong93 benchmark suite. The obtained results show that our algorithm produces
optimal partitioning schedules. 9 Refs.

Accession_Number : 2001(33):2192 COMPENDEX

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