Article : [SHEET164]
Info : INSPEC Answer Number 103 - 22/02/2000
Titre : A.J. YERMAN, J.F. BURGESS, R.O. CARLSON, C.A. NEUGEBAUER, Hot spots caused by voids and cracks in die attach, Proceedings of the 33rd Electronic Components Conference, 16-18 May 1983, pp. 578-582.
Cité dans :[SHEET150] R.O. CARLSON, A.J. YERMAN, J.F. BURGESS, C.A. NEUGEBAUER, Voids, cracks, and hot spots in die attach, Annual Proceedings IEEE Electron Devices Soc, april 1983, pp. 138-141.Auteur : Yerman, A.J.
Source : Proceedings of the 33rd Electronic Components Conference New York, NY, USA: IEEE, 1983.
Pages : 578 - 582 of 623pp.
Lieu : Orlando, FL, USA.
Date : 16-18 May 1983
Sponsors : IEEE; Electron. Ind. Assoc
Price : CCCC 0569-5503/83/0000-0578$01.00
Info : Document Type : Conference Article ; Treatment Code : Practical; Experimental ; Country of Publication : United States
Language : English
Stockage : Thierry LEQUEU
Abstract :
The temperature increase under power dissipation in large
semiconductor chips mounted down with solder containing voids or
cracks is explained in terms of two void types. They are
distinguished on the basis of transient and steady state thermal
resistance measurements, and differ from each other in that for one
the increased thermal resistance is mitigated by a reduced current
density, but not for the other. They have been verified
experimentally, and explain a large range of thermal and electrical
characteristics, such as occur in fatigue cycling.
Accession_Number : 1983:2109527
Reference : 1
[1] : M.W. Smith and A. Poe, "Relating Power Transistor Failure Modes to Post Failure Characteristics", Proc. of Powercon 8, F-1, 1981.
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