Wednesday, June 6, 10:50-12:05, 5F Main Hall

Chairperson: A. Shibib, Agere Systems

                    H. Tadano, Toyota Central Research & Development Labs.

7.1   A Novel Process Technique for Fabricating High Reliable Trench DMOSFETs Using Self-Align Technique and Hydrogen Annealing

        J. Kim, T.M. Roth, S.-G. Kim, D. W. Lee, J.G. Koo and K.-I. Cho

7.2   A High Density, Low On-resistance, Trench Lateral Power MOSFET with a Trench Bottom Source Contact

        N. Fujishima, A. Sugi*, T.Suzuki*, S. Kajiwara*, Y. Nagayasu* and C.A.T. Salama

7.3   An Ultra Dense Trench-Gated Power MOSFET Technology Using the Self-Aligned Process

        J. Zeng, G. Dolny, C. Kocon, R. Stokes, T. Grebs, J. Hao, R. Ridley, J. Benjamin, L. Skurkey, S. Benczkowski, D. Semple, P. Wodarczyk and C. Rexer