Thursday, June 7, 8:30-10:35, 10F Room 1001-3

Chairperson: G. Amaratunga, Cambridge Univ.

                    R.K. Malhan, DENSO

10.1   Breaking the Silicon Limit Using Semi-Insulating Resurf Layers

          R. van Dalen, C. Rochefort and G.A.M. Hurkx

10.2   Lateral Unbalanced Super Junction (USJ) for High Breakdown Voltages in SOI Technology

          R. Ng, F. Udrea, K. Sheng, K. Ueno*, G.A.J. Amaratunga and M. Nishiura*

10.3   A New 800V Lateral MOSFET with Dual Conduction Paths

          D.R. Disney, A.K. Paul, M. Darwish, R. Basecki and V. Rumennik

10.4   Implementation of High-Side, High Voltage RESURF LDMOS in a Sub-Half Micro Smart Power Technology

          R. Zhu, V. Parthasarathy, V. Khemka, A. Bose and T. Roggenbauer

10.5   Lateral Smart-Discrete Process and Devices Based on Thin-Layer Silicon-on-Insulator

          T. Letavic, J. Petruzzello, M. Simpson, J. Curcio, S. Mukherjee, J. Davidson*, S. Peake*, C. Rogers*, P. Rutter*, M. Warwick* and R. Grover*

          Philips Research USA, U.S.A. and *Philips Semiconductors, U.K.