CALL FOR PAPERS

The Integrated Reliability Workshop focuses on reliability tools and approaches in the semiconductor design, development and manufacturing process. It provides a unique environment for envisioning, developing, and sharing reliability technology for present and future semiconductor applications.

The Building-In Reliability concept, or BIR, highlights the importance of an integrated approach to building reliable products, where reliability considerations are integral to the various stages of developing a process, designing a product, and manufacturing in volume.

Wafer level reliability (WLR) was first introduced by this workshop as a methodology for providing timely reliability information early in the manufacturing process, and refers to reliability tests performed as close to the source of potential causes of failure as possible. As such, WLR forms a core activity in BIR. The scope has since evolved to include in-fab tool monitors, reliability modeling and design tools, and reliability test structures.

We invite you to submit a presentation proposal that addresses one or more of the following topics:

Contributors to failure
Failure mechanisms & reliability models (existing, new, anticipated);
Sensitivities to device geometry, materials, and manufacturing.
Reliability test structures
Design, characterization, uses, and data analysis;
Integrated on-chip reliability test systems.
Designing-in reliability (circuits, processes, products)
Methodologies and concepts, modeling,
simulation tools, reliability-driven
design rules and checkers.
Monitors/sensors for reliability learning & control
In processing, assembly, and equipment.
Wafer level reliability
Test and analysis methodologies; In-line monitors;
Relation to circuit element and package tests;
Use and interpretation of WLR data;
Success stories.
Customer product reliability requirements
Reliability evaluation methodologies;Databases;
Reporting systems; Future reliability targets

SUBMISSION DEADLINE:

Received no later than July 7, 1997.

Please submit 15 copies of your two-page (maximum) presentation proposal (including figures). Your submission should state clearly and concisely the results of your work and why they are significant. Representative data or figures that support your proposal are REQUIRED. The proposal must include the title of the presentation, and the name, affiliation, complete return address, telephone and telefax numbers, and e-mail address for each author. Submission should be by post or express mail and NOT telefax. All submissions will be acknowledged. Visual aids for accepted proposals are required by September 15, 1997 for inclusion in the Presentation Handout at the meeting. A written presentation summary will be due by December 1, 1997 for inclusion in the Final Report.

MAIL TO:
Raif S. Hijab, Technical Program Chair, 1997 IRW
Advanced Micro Devices
1 AMD Place, M/S 143.
Sunnyvale, CA 94088-3453, USA

Tel: 408-749-2250
Fax: 408-749-5585
e-mail: raif.hijab@amd.com

ADVANCE REGISTRATION

Advance Registration should be made now to insure your space at the Workshop.

THE WORKSHOP HAS LIMITED SPACE AND YOU ARE ENCOURAGED TO REGISTER EARLY.

The Registration fee is US$900 for IEEE Members and US$950 for non-members, which includes: meals, lodging, and refreshments at the Stanford Sierra Camp; Presentation View Graphs (provided at the Meeting); and the 1997 IRW Final Report (published after the Meeting).

LODGING & FACILITIES

Nestled throughout the pines and cedars along the shoreline of Fallen Leaf Lake, a few miles from South Lake Tahoe, are clusters of 2 and 3 bedroom cabins furnished in the rustic style of an alpine resort. Each cabin cluster is equipped with shared bathroom facilities. All rooms have decks with magnificent views of Fallen Leaf Lake and surrounding Sierra peaks.

The physical isolation of the location and the absence of distractions, such as in-room phones and television sets, encourages extensive interaction among the Workshop attendees.

Lodging is available for meeting attendees only.

JEDEC 14.2 MEETING

The JEDEC 14.2, Wafer Level Reliability Standards Committee, meeting will be held immediately after the Workshop at the Stanford Sierra Camp on Thursday afternoon and Friday morning. Members, alternates, and guests are welcome. The cost for the accommodations is $160.00, which includes Thursday night dinner and lodging and Friday breakfast and lunch. All attendees must leave the camp after lunch on Friday. If you have any questions or if you want to become a member of JC-14.2, please call the JEDEC office at (703) 907-7558.

HISTORY

The Wafer Level Reliability Workshop was initiated in 1982 through the efforts of O. D. "Bud" Trapp, of Technology Associates, and the active support and encouragement of DARPA (Defense Advanced Research Projects Agency). This support continued for the first eight years of the Workshop and included active support and involvement of the Stanford University Integrated Circuits Laboratory and the University of California, Berkeley, Dept. of Electrical Engineering and Computer Sciences. After DARPA sponsorship ended, Bud Trapp continued the direction of the Workshop until 1991 after which time he requested that sponsorship and management be assumed by an appropriate professional association. The IEEE accepted this responsibility in 1992. In 1993, the name of the Workshop was changed to the Integrated Reliability Workshop. This change reflects the enlarged scope of the Workshop, the integrated nature of reliability in the manufacture of semiconductor products, and the need for a broader and a more comprehensive approach to reliability engineering.

SPONSORS

The International Integrated Reliability Workshop is sponsored and managed by the IEEE Electron Device Society and the IEEE Reliability Society through the Board of Directors of the International Reliability Physics Symposium.