Defect Reliability Statistics with Redundancy

Defect Reliability Statistics with Redundancy Power and intrinsic wearout have begun to limit the effectiveness and increase the costs of burn-in for high-performance silicon processes. This tutorial covers approaches and models useful in controlling infant mortality today. Power management in burn-in, fault-tolerant chip design, population slicing, etc. will be discussed.

C. Glenn Shirley

Glenn Shirley is Manager of Sort/Test Technology Development Q&R at Intel in Hillsboro, Oregon. He has worked for Intel for 18 years in quality and reliability, most recently, developing test and burn in methodologies. Prior to Intel he worked for Motorola and U.S. Steel, and as a post-doc at Carnegie-Mellon University. He has a Ph.D. in physics from Arizona State University, and a M.Sc. in physics from the University of Melbourne in Australia. He came to the U.S. in 1970 from Australia.