Introduction to Predictive Wafer Level Reliability

Assuring IC reliability is even more challenging today with new materials and higher than ever levels of material stress. Wafer Level Reliability (WLR) is one tool that can help meet this challenge. Traditional WLR approaches have emphasized test speed over quality of data. This tutorial will introduce Predictive WLR and show how proper attention to the underlying reliability physics can yield WLR that provides quantitative data similar to packaged-level tests in a much shorter time. This predictive WLR supports process monitoring, rapid qualification and development. We describe the theoretical approach needed to maximize the quality of WLR data with examples of Cu/low-k electromigration and vias, ultra-thin oxide breakdown, deep submicron hot-carriers, plasma damage and mobile ions. These technical examples show the features and utility of a WLR that is optimized for predictability and not just speed.

Eric S. Snyder

Eric S. Snyder is an officer and founder of Sandia Technologies, Inc. which provides WLR solutions world-wide. Prior to founding Sandia Technologies, Mr. Snyder spent 7 years as a Senior Member of the Technical Staff at Sandia National Laboratories with the Reliability Physics Department. Previously, he worked for IBM and Intel. He serves on the Board of Directors of IPRS, was the 2001 Technical Program Chair of the IRPS, the 1999 General Chair of the IRW and the JEDEC 14.2 hot carrier standards chair and has served on the FSA/JEDEC qualification committee. He received a 1994 R&D 100 Award for the invention of the self-stressing test structures and has authored numerous reliability papers including 3 best paper awards. He has taught wafer level reliability tutorials at IRPS, IRW and ICMTS reliability conferences as well as a graduate class in Integrated Circuit Reliability at the University of New Mexico. He received a M.S. in electrical engineering from the Georgia Institute of Technology