Comparison of Soft Errors in Protected and Unprotected Processors

Soft error vulnerability for memories is established. Now, the logic part of chips is just as vulnerable, receiving attention by relatively few. Protection of logic is different from memories. We will demonstrate radiation test results for a SPARC chip with and without protection demonstrating sensitivity to and protection from soft errors.

Peter Rohr

Dr. Peter Rohr has over 30 years experience in hi-tech electronics in companies such as IBM, TRW, Hughes Electronics, Analog Devices, Silicon Compilers, Teradyne, Mentor Graphics and Sagantec with senior management positions for applications engineering, sales, marketing and business development in several European countries and the United States. As a Member of the Graduate Faculty in Electrical Engineering at LSU, he has lectured on analog circuit design and semiconductor physics. As a Consultant he has conducted workshops on deep sub-micron and VLS IC DFT design methodologies. He is now Vice President in Business Development at iRoC Technologies in the field of fault tolerant and robust VLS ICs. Dr. Rohr has authored some papers on VLSI issues and is the author of the book “Hard IP, an introduction to increasing ROI for VLSI Chip designs” published in 2001. Dr. Rohr holds the B.S., M.S. and Ph.D. in electrical engineering with emphasis in semiconductor physics and device modeling from the Universities of Vermont and Florida. He speaks several foreign languages.