Introduction to Semiconductor Reliability

Tim Rost, Vijay Reddy

Texas Instruments

As increasing investments are made in VLSI technology and development, it becomes essential that semiconductor processes and IC designs have reliability issues addressed prior to volume manufacturing. Ideally, reliability issues would be addressed and corrected during the design process. This tutorial provides the motivation for understanding semiconductor reliability issues, a basic review of reliability wearout mechanisms, a discussion of how reliability mechanisms can be checked and corrected in the design phase, and how process technologies such as Cu interconnects and low-K dielectrics influence reliability design guidelines. This tutorial will provide the foundation to allow you to build technical depth in the areas of specific interest throughout the rest of the symposium.

Rost, Tim

Tim Rost is a process integration manager in Silicon Technology Development at Texas Instruments. Tim received B.A. degrees in Physics and Computer Science from Gustavus Adolphus College in St. Peter, Minnesota in 1986. He then received Masters and Ph.D. degrees from Rice University in Electrical and Computer Engineering in 1990, and 1991, respectively. After joining Texas Instruments in Dallas, Tim worked on various aspects of semiconductor reliability physics, eventually managing the device reliability group. Tim is a Senior Member Emeritus of the Technical Staff at Texas Instruments. He has served in various capacities in the IEEE, most notably as the Dallas Chapter Chair and on the ADCOM committee for the Reliability Society. He has also served in various positions in the IRPS, most recently as the Tutorials chair in 2001. Tim was selected to receive the IEEE's Third Millenium medal in 2000.

Reddy, Vijay

Vijay Reddy is a Member of the Group Technical Staff at Texas Instruments, Dallas, Texas. He received his Ph.D. in Electrical Engineering in 1994 from the University of Texas at Austin. He joined TI in 1994 and has worked on dielectric reliability, ESD, Latch-up, transistor reliability, and mobile ion testing of logic and DRAM technologies. Since 1998 he has focused on transistor and circuit reliability in sub-0.13um logic and embedded memory technologies. More recently his activities have included product reliability and test methodologies for defect screening.