Co-Chairs: Bob Knoell, Visteon and Dimitar Dimitrov, AMD

1.1 RELIABILITY DEGRADATION OF HIGH DENSITY DRAM CELL TRANSISTOR JUNCTION LEAKAGE CURRENT INDUCED BY BAND-TO-DEFECT TUNNELING UNDER THE OFF-STATE BIAS-TEMPERATURE STRESS—Y.P. Kim, Y.W. Park, J.T. Moon, and S.U. Kim, Samsung Electronics Co., Yongin-City, Korea

The band-to-defect tunneling (BDT) induced junction leakage current of high density DRAM cell transistor under the off-state bias-temperature (B-T) stress is investigated. The BDT leakage current is found to be the most critical limit in DRAM scaling, and the new off-state B-T stress is suggested to assess reliability degradation of the future thin gate oxide DRAM transistor.

1.2 A NEW METHOD FOR PREDICTING DISTRIBUTION OF DRAM RETENTION TIME—Y. Mori, R. Yamada, S. Kamohara, M. Moniwa, K. Ohyu, and T. Yamanaka, Hitachi, Ltd., Tokyo, Japan

A new method for predicting the distribution of DRAM retention time by using Test Element Groups constructed of memory cells is shown. The main retention time distribution is extracted from the structure and the measurement condition to depict the limiting defect tail is described.

1.3 IS PRODUCT SCREEN ENOUGH TO GUARANTEE LOW FAILURE RATE FOR THE CUSTOMER?—M.W. Ruprecht, Infineon Technologies, Essex Jct., VT, G. La Rosa, and R.G. Filippi, IBM Microelectronics, Hopewell Junction, NY

An in-line monitoring process methodology to prevent wear-out fails during the product lifetime for deep-sub micron technology is presented. Standby current fails from DRAM modules caused by PMOSFET Hot Carrier degradation is shown to be a product failure mechanism, requiring optimized in-line monitoring.

1.4 ANALYSIS OF ERRATIC BITS IN FLASH MEMORIES—A. Chimenton, P. Pellati, and P. Olivo, Università di Ferrara, Ferrara, Italy

New experimental results concerning erratic bits in FLASH memories are presented. They are obtained by tracking the threshold voltage dynamics during erase operations, providing insight to their physical nature.The particular shape of the erase curves so obtained, are used to derive a direct link between the amplitude of erratic threshold variations and that of the equivalent barrier height controlling FN injection.

1.5 INDIVIDUAL CELL MEASURING METHOD FOR FERAM RETENTION TESTING—N. Tanabe, H. Koike, T. Miwa, J. Yamada, A. Seike, N. Kasai, H. Toyoshima, and H. Hada, NEC Corp., Kanagawa, Japan

A novel test structure measures the read signal voltages of individual cells and records their addresses, to establish long-term data retention of an FeRAM chip is discussed. The expected retention times for all bits are estimated to extrapolate the relation between the read signal voltage and the retention time. The estimation shows that the upper limit of the retention time for each bit has a Gaussian distribution.

1.6 YIELD ENHANCEMENT AND YIELD MANAGEMENT OF SILICON FOUNDRIES USING IDDQ "STRESS CURRENT SIGNATURE"—M. Rubin, S. Natan, and D. Leary, Agilent Technologies, Fort Collins, CO

A novel Iddq analysis technique, using a "Stress Current Signature" is correlated with reliability failures. Case studies involving foundry yield management and failure analysis are described.

1.7 DYNAMIC VOLTAGE STRESSING APPLYING IN THE REDUCTION OF THE EARLY FAILURE RATE—C.-Y. Tsao, R.Y. Shiue, C.C. Ting, Y.S. Huang, Y.C. Lin, and J. Yue, TSMC, Hsin-Chu, Taiwan

Dynamic voltage stress (DVS) is used to improve the early life failure rate (ELFR). The ELFR reduction is shown to be > 60% when a delta source to bulk current screening is integrated with DVS. This enables a burn-in reduction methodology.

Tuesday, May 1, 2:00 p.m., Parallel Session, Great Hall North

PROCESS & RELIABILITY INTERACTIONS (Session 2A)

Co-Chairs: Fred Kuper, Philips Semiconductors and Walter Riordan, Intel

2A.1 A STUDY OF FORMATION AND FAILURE MECHANISM OF CMP SCRATCH INDUCED DEFECTS ON ILD IN A WDAMASCENE INTERCONNECT SRAM CELL—S.-M. Jung, H.S. Kang, W.S. Cho, J.S. Uom, Y.J. Bae, K.S. Yoo, G.Y. Kim, and K.T. Kim, Samsung Electronics Co., Yongin-City, Korea

The formation mechanism of CMP scratches and the failure mechanism under the electrical stress in a conventional double layer ILD CMP process is analyzed and modeled using 8M bit SRAM . It was found that the CMP scratches could cause not only an initial failure but also a fatal long-term reliability failure similar to the time dependent dielectric breakdown. New CMP scratch free W-damascene technology was developed.

2A.2 THE EFFECTS OF STI PROCESS PARAMETERS ON THE INTEGRITY OF DUAL GATE OXIDES—H. Lim, S.-J. Lee, J. M. Youn, T.-H. Ha, J.-H. Lim, B.-H. Choi, K.-J. Kim, and K.T. Kim, Samsung Electronics Co., Yongin-City, Korea

The thick oxide constructed by dual gate oxide process shows a larger susceptibility to STI process parameters than single-step-grown thin oxide due to the wet etch before 2nd oxidation. It was found that the Deposition/Sputter ratio and the densification temperature of HDP oxide are critical parameters for the stress at the STI boundary and charge-to-breakdown characteristics of dual gate oxides.

2A.3 IMPROVEMENT IN RETENTION RELIABILITY OF SONOS NONVOLATILE MEMORY DEVICES BY TWO-STEP HIGH TEMPERATURE DEUTERIUM ANNEALS—J. Bu and M.H. White, Lehigh University, Bethlehem, PA

Two-step high temperature deuterium anneals applied in SONOS device fabrication, improves the retention reliability and endurance characteristics over traditional hydrogen anneals. Electrical characterization shows deuterium-annealed SONOS devices have nearly one order of magnitude longer retention time than hydrogen-annealed devices after 10⁷ erase/write cycles at 85 °C to providea 0.5 V detection window.

2A.4 DATA RETENTION FAILURE IN NOR FLASH MEMORY CELLS—W.H. Lee, D.-K. Lee, Y.-M. Park, K.-S. Kim, K.O. Ahn, and K.-D. Suh, Samsung Electronics Co., Kiheung-Eup, South Korea

Data retention failures due to non-optimized processes in NOR-type flash memory devices are presented. Contrary to charge leakage through defective oxide dielectric surrounding the floating gate, the data loss observed depends on whether the bit line contact is close to the cell or not. Based on experimental results, sodium movement in side wall spacers is established as an origin for the data retention failure in NOR-type flash memory.

2A.5 A NEW CONDUCTION MECHANISM FOR THE ANOMALOUS CELLS IN THIN OXIDES FLASH EEPROMS—A. Modelli, F. Gilardoni, STMicroelectronics, Agrate Brianza, Italy, D. Ielmini, Politecnico di Milano, Milano, Italy, and A.S. Spinelli, Università degli Studi dell'Insubria, Como, Italy

The temperature dependence of the anomalous leakage current in the tail cells of flash memory is investigated on arrays with different oxide thickness. It is shown that both the conduction mechanism and the annealing kinetics of the leakage current change when the thickness is reduced below about 8 nm, becoming independent of temperature. The microscopic conduction of the tail cells is analyzed to investigate the conduction model in thin oxides.

2A.6 N-CHANNEL VERSUS P-CHANNEL FLASH EEPROM-WHICH ONE HAS BETTER RELIABILITIES—S.S. Chung, S.T. Liaw, Z.H. Ho, National Chiao Tung Univ., Hsinchu, Taiwan, C.J. Lin, TSMC, Hsinchu, Taiwan, C.M. Yih, National Chiao Tung Univ., Hsinchu, Taiwan, D.S. Kuo, and M.S. Liang, TSMC, Hsinchu, Taiwan

In this paper, a comprehensive study of n- and p-channel flash cells in terms of various reliability issues is presented. Results show that the cell speed, endurance, and gate/read disturb of p-channel cell is much better than those of n-channel cells; except that p-channel cell should use the DINOR structure to prevent drain disturb. As a whole, the p-channel cell features high speed, lower power, and better reliability. These make it more attractive for future applications.

2A.7 NEW TECHNIQUE FOR FAST CHARACTERIZATION OF SILC DISTRIBUTION IN FLASH ARRAYS—D. Ielmini, Politecnico di Milano, Milano, Italy, A.S. Spinelli, Università degli Studi dell'Insubria, Como, Italy, A.L. Lacaita, Politecnico di Milano, Milano, Italy, L. Confalonieri, and A. Visconti, STMicroelectronics, Agrate Brianza, Italy

The extraction of SILC distributions in Flash memory cells can lead to an improved understanding of the cell leakage mechanism, as well as to more refined reliability evaluations. A new technique for the extraction of cell SILC is presented, which does not require the tracking of the V_T evolution of individual cells, but only the cumulative behavior of the array. Validation of the technique with simulation of the cumulative distribution of V_T and of failure time is also carried out.

Co-Chairs: Danelle Tanner, Sandia National Labs and Susanne Arney, Lucent Technologies

2B.1 RELIABILITY OF A MEMS TORSIONAL RATCHETING ACTUATOR—D.M. Tanner, S.M. Barnes, J.A Walraven, and N.F. Smith, Sandia National Labs, Albuquerque, NM

A new surface-micromachined actuator, the Torsional Ratcheting Actuator (TRA) has undergone reliability testing and failure analysis. Tests were performed at three frequencies (333 Hz, 1000 Hz, and 3000 Hz). A failure mechanism (observed in the guide dimples) was determined to be adhesion of rubbing polysilicon surfaces.

2B.2 FULL THREE-DIMENSIONAL MOTION CHARACTERIZATION OF A GIMBALLED ELECTROSTATIC MICROACTUATOR—C. Rembe, UC Berkeley, Berkeley, CA, L. Muller, Network Photonics, Inc., Boulder, CO, R.S. Muller, A.P. Pisano, and R.T. Howe, UC Berkeley, Berkeley, CA

We have developed a computer-controlled stroboscopic interferometer for characterization of rapid dynamic processes in Microelectromechanical Systems (MEMS). Digital image processing is used to achieve high-resolution measurement of out-of-plane motion as well as of in-plane motion. The nonlinear three-dimensional dynamic behavior of a gimballed electrostatic actuator for a hard disk drive is investigated.

2B.3 NON-DESTRUCTIVE RESONANT FREQUENCY MEASUREMENT ON MEMS ACTUATORS—N.F. Smith, D.M. Tanner, and S.L. Miller, Sandia National Labs, Albuquerque, NM

A method has been developed to determine the resonant frequency of MEMS actuators. This technique is non-destructive to the device because it does not require the device be stimulated at resonance. The technique has been applied to several devices and compared to results obtained from traditional techniques.

2B.4 SIZE EFFECT ON THE MECHANICAL PROPERTIES AND RELIABILITY ANALYSIS OF MICROFABRICATED POLYSILICON THIN FILMS—J.N. Ding, Y.S. Meng, and S.Z. Wen, Tsinghua Univ., Beijing, PR China

A new microtensile test device using a magnetic-solenoid force actuator was developed to evaluate the mechanical properties of microfabricated polysilicon thin films. Statistical analysis of the specimen size effects on the tensile strength was investigated. The recommendation for design with strain criterion of fracture in polysilicon thin films was given.

Tuesday, May 1, 4:05 p.m., Parallel Session, Scotland

PACKAGING AND ASSEMBLY (Session 2C)

Co-Chairs: Tom Moore, Texas Instruments and S. Sidharth, AMD

2C.1 (INVITED, ESREF BEST PAPER) A SIMPLE MODEL FOR THE MODE I POPCORN EFFECT FOR IC PACKAGES—P. Alpern, K.C. Lee, Infineon Technologies, R. Dudek, IZM, R. Tigner, Infineon Technologies

2C.2 IMPROVING CORROSION-RESISTANCE OF SILICON-GLASS MICROPACKAGES USING BORON DOPING AND/OR SELF-INDUCED GALVANIC BIAS—B.H. Stark, M.R. Dokmeci, T.J. Harpster, and K. Najafi, Univ. of Michigan, Ann Arbor, MI

MEMS intended for use in harsh environments, such as the human body, use micro-packages to maintain their integrity. Two novel methods are reported for improving the corrosion resistance of glass-silicon micro-packages in high temperature saline soak tests. By using boron doping and/or galvanic biasing, the dissolution of polysilicon can be reduced by several orders of magnitude.

2C.3 A FATIGUE THEORY FOR SOLDERS—S. Wen and L.M. Keer, Northwestern Univ., Evanston, IL

A fatigue theory is presented for solders. It is assumed that resolved shear stress causes the formation of persistent slip bands (PSB's). Mura's theory of crack initiation is adopted for the microcrack formation within the PSB's. Grains with different crystallographic orientation fail at different numbers of cycles. By a process of percolation, the structure reaches failure when the total portion of failed grains reaches a critical value.

2C.4 A NEW MECHANICAL CONCEPT AND ITS APPLICATION IN RELIABILITY EVALUATION OF SOLDER JOINT CONNECTIONS USED IN ELECTRONIC PACKAGING—X. Ma, CEPREI, Guangzhou, PR China, Y. Qian, Harbin Institute of Tech., Harbin, PR China, and X. Zhang, CEPREI, Guangzhou, PR China

A new mechanical concept, relative damage stress (RDS) is presented to describe the failure behavior of solder joints during accelerated thermal fatigue testing of board-level assemblies. RDS encompasses the Mises equivalent stress, which governs plasticity of solder alloy, the stress triaxiality, which reflects the assembly constraint, the Poisson's ratio, and the yield stress, which reflects the temperature dependence of material properties. Therefore, we can directly compare the RDS at different temperatures during temperature cycling, and recommend improvements in the design of accelerated thermal fatigue tests.

Wednesday, May 2, 8:00 a.m., Parallel Session, Great Hall North

OXIDE I (Session 3A)

Co-Chairs: Robin Degraeve, IMEC and Paul Nicollian, Texas Instruments

3A.1 (INVITED) DEFECT GENERATION AND RELIABILITY OF ULTRA-THIN SILICON DIOXIDE AT LOW VOLTAGE—J.H. Stathis and D.J. DiMaria, IBM, Yorktown Hgts., NY

The reliability of ultrathin SiO₂ layers and the consequences for continued thickness scaling are a critical technology issue. We review the defect generation and breakdown physics of ultrathin oxides at low voltages. Although the defect generation rate decreases exponentially as supply voltage is reduced, tunneling currents increase exponentially with decreasing oxide thickness, leading to a diminishing margin for reliability.

3A.2 (INVITED) IDENTIFICATION OF ATOMIC SCALE DEFECTS INVOLVED IN OXIDE LEAKAGE CURRENTS—P.M. Lenahan, J.J. Mele, J. Campbell, A. Kang, Penn State Univ., University Park, PA, R.K. Lowry, D. Woodbury, Intersil, Palm Bay, FL, and S.T. Liu, Honeywell Corp., Plymouth, MN

We identify atomic scale defects involved in Stress-Induced-Leakage-Currents (SILC) with a combination of electron spin resonance (ESR) and electrical measurements. In addition, we propose a model of SILC based upon these defects and the fundamental principles of the statistical mechanics of defects in solids.

3A.3 NANOSCALE OBSERVATIONS OF THE ELECTRICAL CONDUCTION OF ULTRA THIN SiO₂ FILMS WITH CONDUCTING ATOMIC FORCE MICROSCOPY—M. Porti, M. Nafría, X. Aymerich, Univ. Autònoma de Barcelona, Bellaterra, Spain, A. Olbrich, and B. Ebersberger, Infineon Technologies AG, Munich, Germany

For the first time, a Conducting Atomic Force Microscope (C-AFM) is used to study both the pre- and post-breakdown conduction of a single SiO₂ breakdown spot. The results provide direct evidence of the nanometer scale nature of the degradation and breakdown

3A.4 SOFTENING OF BREAKDOWN IN ULTRA-THIN GATE OXIDE NMOSFETS AT LOW INVERSION LAYER DENSITY—S. Lombardo, Consiglio Nazionale delle Ricerche, Catania, Italy, F. Crupi, Università di Messina, Messina, Italy, and J.H. Stathis, IBM, Yorktown Hgts, NY

The post breakdown I-V characteristics of ultra-thin gate oxides subjected to constant voltage Fowler-Nordheim stress in nMOSFETs were investigated. It is shown that under the same stress field conditions the oxide I-V characteristics after the breakdown event strongly depend on the density of electrons in the inversion layer.

3A.5 CALCULATING THE ERROR IN LONG TERM OXIDE RELIABILITY ESTIMATES—B.P. Linder, J.H. Stathis, and D.J. Frank, IBM, Yorktown Hgts, NY

Ultra-thin oxide reliability is a critical issue in integrated circuit scaling. Oxide reliability may actually prevent future scaling of SiO₂ gate dielectrics. The statistical error in long term oxide reliability projections has not been cohesively treated. Using Monte Carlo techniques, the amount of uncertainty in reliability projections is calculated. Analyzing typical published data, the uncertainty in the failure rate is greater than an order of magnitude.

Wednesday, May 2, 10:30 a.m., Parallel Session, Great Hall North

WLR FOR INTERCONNECTS (Session 3B)

Co-Chairs: J. Joseph Clement, Sandia National Labs and Armin Fischer, Infineon Technologies

3B.1 COMPARISON OF ISOTHERMAL, CONSTANT CURRENTAND SWEAT WAFER LEVEL EM TESTING METHODS—T. Lee, D. Tibel, and T. Sullivan, IBM Microelectronics, Essex Jct., VT

Data are presented from three wafer level test techniques _ Isothermal, Constant Current, and SWEAT. The three techniques are compared and evaluated.

3B.2 REAL CASE STUDY FOR ISOTHERMAL EM TEST AS A PROCESS CONTROL METHODOLOGY—S.-Y. Lee, J.B. Lai, S.C. Lee, L.H. Chu, R.Y. Shiue, and J. Yue, TSMC, Hsin-Chu, Taiwan

The failure mechanism observed in fast wafer-level isothermal EM tests is found to be similar to that in conventional package EM tests, when the appropriate failure criterion is used. The capability of the isothermal test to detect metal reliability problems is shown to correlate well with conventional long-term tests in real case studies.

3B.3 EXPERIMENTAL COMPARISON OF WAFER LEVEL RELIABILITY (WLR) AND PACKAGED ELECTROMIGRATION TESTS—C. Ryu, T.-L. Tsai, A. Rogers, C. Jesse, T. Brozek, D. Zarr, M. Adamson, S. Nayak, and S. Nayak, Motorola SPS, Chandler, AZ

The sensitivity of a wafer level reliability electromigration (WLR EM) test was investigated for various backend process variations. Although the WLR EM test uses very different test methodology from conventional long-term packaged EM testing, the WLR EM data was found to have good correlation with the packaged EM results.

3B.4 COMPARISON OF VIA/LINE PACKAGE LEVEL VS. WAFER LEVEL RESULTS—D. Tibel and T. Sullivan, IBM Microelectronics, Essex Jct., VT

In this work, we demonstrate that lifetime predictions can be made from isothermal wafer level test results using modeling parameters obtained from package level tests. Comparison of the acceleration factor between the wafer and package level tests yields very good agreement. The kinetics determined from both tests are discussed.

Wednesday, May 2, 8:00 a.m., Parallel Session, Scotland

OPTOELECTRONICS & COMPOUND SEMICONDUCTOR (Session 3C)

Co-Chairs: Sammy Kayali, JPL and J.J. Liou, University of Central Florida

3C.1 ACCELERATED STRESSING AND DEGRADATION MECHANISMS FOR SI-BASED PHOTO-EMITTERS—A. Chatterjee and B.L. Bhuva, Vanderbilt Univ., Nashville, TN

Light emitters are stressed with ac, dc, and temperature. The results clearly show that the effects of ac and temperature stressing on light emission are negligible. DC stressing results in light coalescence with total light emission coming out of the junction remain constant. The light coalescence is also a strong function of the device layout. Reliability of light emission is extremely good under all the stress conditions considered for applications of on-chip interconnect.

3C.2 LOW-TEMPERATURE, HIGH-CURRENT LIFETESTS ON INP-BASED HBT'S—B.M. Paine, Hughes S&C Co., Los Angeles, CA, S. Thomas III, HRL Labs, Malibu, CA, and M.J. Delaney, Hughes S&C Co., Los Angeles, CA

Lifetests have been conducted on discrete InP HBTs, at relatively low temperatures and high collector currents. The goal is to test for low-activation-energy failure mechanisms that may have been undetectable in conventional lifetests. Analysis indicates relatively low probability of failure in typical applications.

3C.3 DEGRADATION CHARACTERISTICS OF AlGaN/GaN HIGH ELECTRON MOBILITY TRANSISTORS (HEMTS)—H. Kim, B. Green, V. Tilak, H. Cha, J.A. Smart, J.R. Shealy, and L.F. Eastman, Cornell University, Ithaca, NY

Results of reliability tests on AlGaN/GaN power HEMT's are presented for the first time. The degradation characteristics of these devices were measured under various stress conditions such as reverse gate bias, RF overdrive, and elevated temperature storage. The devices demonstrated good reliabilities for high power and high temperature applications under high stress conditions.

Wednesday, May 2, 10:30 a.m., Parallel Session, Scotland

ESD/LATCHUP (Session 3D)

Co-Chairs: Robert Gauthier, IBM and Jeremy Smith, Motorola

3D.1 CHARACTERIZATION AND INVESTIGATION OF THE INTERACTION BETWEEN HOT ELECTRON AND ELECTROSTATIC DISCHARGE STRESSES USING NMOS DEVICES IN 0.13µM CMOS TECHNOLOGY—A. Salman, George Mason Univ., Fairfax, VA, R. Gauthier*, S. Furkay*, M. Muhammad, GCI, Parsippany, NJ, C. Putnam*, VT, D. Ioannou, George Mason Univ., Fairfax, VA, P. Nguyen*, and W. Stadler, Infineon Technologies, Munich, Germany
        *IBM Microelectronics, Essex Jct., VT

The high-current characteristics encountered during electrostatic discharge (ESD) events using a NMOS/LNPN protection device in a 0.13 µm CMOS technology are investigated for different device parameters. The effect of silicide blocking and hot electron (HE) shifts on the second breakdown current of the NMOS devices are studied for both silicided and non-silicided devices. The impact of non-destructive ESD stressing on HE shifts is also studied for the same devices.

3D.2 NON-UNIFORM BIPOLAR CONDUCTION IN SINGLE FINGER NMOS TRANSISTORS AND IMPLICATIONS FOR DEEP SUBMICRON ESD DESIGN—K.-H. Oh, Stanford Univ., Stanford, CA, C. Duvvury, C. Salling, Texas Instruments, Dallas, TX, K. Banerjee, and R.W. Dutton, Stanford Univ., Stanford, CA

A detailed study of the non-uniform bipolar conduction phenomenon in single finger NMOS transistors and its implications for deep submicron ESD design is investigated. The impact of substrate bias to overcome this effect to achieve practical designs has been demonstrated. Additionally, a new concept of intrinsic second breakdown triggering current is introduced, which can be used to generate efficient ESD design guidelines for deep submicron processes.

3D.3 ADVANCED 2D LATCH-UP DEVICE SIMULATION-A POWERFUL TOOL DURING DEVELOPMENT IN THE PRE-SILICON PHASE—S. Bargstädt-Franke and K. Oettinger, Infineon Technologies AG, Munich, Germany

Parasitic device characteristics which change the latch-up sensitivity during the early technology development phase is not easily and accurately simulated with today's device simulators. In this paper, calibrated 2-D simulations are used for optimizing the technology according to these parasitic effects, yielding to an area optimization which helps to reduce the chip size/cost.

3D.4 AN ANALYSIS OF BIPOLAR BREAKDOWN AND ITS APPLICATION TO THE DESIGN OF ESD PROTECTION CIRCUITS—S. Joshi, Univ. of Ill, Urbana-Champaign, Urbana, IL, R. Iday, Motorola, Tempe, AZ, P. Givelinz, Motorola, Toulouse, France, and E. Rosenbaum, Univ. of Ill, Urbana-Champaign, Urbana, IL

Analytical expressions for the breakdown voltage of an NPN with a resistively grounded base, both with and without the zener diode trigger which is used in a common ESD protection circuit, are presented for the first time. The results are used to explain anomalous behavior in the I-V curve of the protection circuit and to achieve a more efficient ESD protection circuit design.

3D.5 PARASITIC BIPOLAR TRANSISTOR MODEL USING GENERATED-HOLE-DEPENDENT BASE RESISTANCE—K. Suzuki, H. Anzai, T. Nomura, and S. Satoh, Fujitsu Ltd., Atsugi, Japan

Injected electrons are known to modulate base resistance but this is found to not be the case during snapback due to the electric field associated with injected electrons being compensated by the holes generated in the drain region. A new model is developed that depends on generated holes as well as injected electrons.

3D.6 DESIGN AND ANALYSIS OF NEW PROTECTION STRUCTURES FOR SMART POWER TECHNOLOGY WITH CONTROLLED TRIGGER AND HOLDING VOLTAGE—V. De Heyn, G. Groeseneken, B. Keppens, N. Mahadeva Iyer, IMEC, Leuven, Belgium, L. Vacaresse, and G. Gallopyn, Alcatel Microelectronics, Oudenaarde, Belgium

An adjustable trigger and holding voltage device is designed in a smart power technology by changing the lateral bipolar base distance. The layout variation that controls the holding voltage also leads to a different snapback mechanism and a different current flow through the device. Excellent ESD capabilities of 16mA/um and 20mA/um of device width have been achieved.

Wednesday, May 2, 2:00 p.m., Parallel Session, Great Hall North

PRODUCT RELIABILITY II (Session 4A)

Co-Chairs: Rich Blish, AMD and Courtney Black, Silicon Bandwidth

4A.1 HISTORICAL TREND IN ALPHA-PARTICLE INDUCED SOFT ERROR RATES OF THE ALPHA MICROPROCESSOR—N. Seifert, D. Moyer, and N. Leland, Compaq Computer, Shrewsbury, MA

The historical trend in Alpha-Particle induced soft-error rates of Alpha microprocessors fabricated in different technologies demonstrates the increasing importance of failures occurring in the core logic to the overall chip-level FIT rate. The impact of scaling of the operating voltage and of the process on the SER is discussed.

4A.2 A RELIABILITY METHODOLOGY FOR LOW TEMPERATURE DATA RETENTION IN FLOATING GATE NON-VOLATILE MEMORIES—P.J. Kuhn, A. Hoefler, T.S. Harp, B.E. Hornung, R.E. Paulsen, D. Burnett, and J.M. Higman, Motorola, Austin, TX

A reliability assessment methodology consisting of a statistical model and experiments is used to evaluate the leakage mechanism responsible for Low Temperature Data Retention in floating gate non-volatile memories. The nature of the leakage mechanism and the methodology necessary to observe and accurately assess this phenomenon are described.

4A.3 HIGH-PERFORMANCE CHIP RELIABILITY FROM SHORT-TIME-TESTS: STATISTICAL MODELS FOR OPTICAL INTERCONNECT AND HCI/TDDB/NBTI DEEP-SUBMICRON TRANSISTOR FAILURES—A. Haggag, K. Hess, W. McMahon, K. Cheng, J. Lee, and J. Joseph, Univ. of Illinois, Urbana, IL

The failure-time distribution of both deep-submicron transistors and optical interconnects owing to the presence of a common defect activation energy distribution is derived. Short-time device degrdation may be used to extract the tails of this semi-symmetric distribution. Through the application of novel reliability qualification rules, "latent failures" can be avoided by design changes implemented for reliability.

4A.4 AN APPLICATION-SPECIFIC USAGE MODEL FOR FLASH MEMORY READ DISTURB RELIABILITY—T.S. Harp, P.J. Kuhn, J.M. Higman, R.E. Paulsen, and B.E. Hornung, Motorola, Austin, TX

We present a method to account for customer applications or usage profiles when evaluating read disturb reliability of flash memory products. Monte Carlo simulations explore reliability of read disturb mechanisms following Weibull and LogNormal statistics vs. application. Experimental data supporting the model will be available for final paper.

Co-Chairs: Jacob Phang, National Univ. of Singapore and Travis Eiles, Intel

4B.1 CASE HISTORY: NOVEL FA TECHNIQUES USED TO RECOVER EEPROM DATA FROM THE SWISSAIR 111 CRASH—R. Haythornthwaite, A. Earle, and A. Rahal, Chipworks Inc., Ottawa, Canada

The pre-crash memory contents were successfully read from a corroded and damaged 256K EEPROM from Swissair 111. High temperatures, etchants and SEM radiation were forbidden to preserve data. Wires were attached to missing bond pads using epoxy before FIB tracks were laid to the bonds and FIB repairs made.

4B.2 NOVEL NONDESTRUCTIVE AND NON-ELECTRICAL-CONTACT FAILURE ANALYSIS TECHNIQUE - SCANNING LASER-SQUID MICROSCOPY—K. Nikawa and S. Inoue, NEC Corp., Kawasaki, Japan

A novel failure analysis technique that can localize electrical defects has been developed. In this technique, the magnetic field produced by a laser-beam-induced current is detected by high Tc DC SQUIDs. The spatial resolution has been demonstrated to be better than 1.3.

4B.3 ANALYSIS OF VIA-VOID GENERATION MECHANISM FOR GIGA-BIT-SCALE DRAM—D.H. Kim, J.S. Park, B.C. Kim, S.C. Lee, M.K. Bae, J.W. Nam, I.S. Park, H.Y. Kim, T.K. Kim, J.S. Kim, Y.J. Park, J.I. Hong, and J.W. Park, Samsung Electronics Co., Younin-Si, Korea

The reaction of Al and stress enhancement after interconnection process induce volume shrinkage of the interconnection line. This is the generation mechanism of the via-void. The void-free, high reliable gigabit-scale DRAM could be realized when the reaction of Al and the interconnection stress are minimized.

4B.4 STUDY OF METAL IMPURITIES BEHAVIOR DUE TO DIFFERENCE IN ISOLATION STRUCTURE ON ULSI DEVICES—K. Matsukawa, Y. Kimura, H. Yamamoto, and Y. Mashiko, Mitsubishi Electric Corp., Itami, Japan

We have shown that the behavior of metal impurities such as Cu and Ni is different due to the difference of isolation structure. It’s found that Cu is trapped easily at STI, and Ni is trapped in bulk micro defects (BMD) regardless of isolation structure.

4B.5 HIGH SRAM STANDBY CURRENT DUE TO THE PRINTING OF SPURIOUS IMAGES—S. Tang, M. Mims, T. Cynkar, P.J. Marcoux, and D. Eaton, Agilent Technologies, Fort Collins, CO

Photoemission microscopy of a 2Mbit SRAM identified a physical pattern of quiescent current (IDDq) failures on the regular array of this circuit. The pattern of IDDq failures correlated almost exactly with identifying marks on the edge of the SRAM gate reticle. This discovery led to the detection of contamination of the photolithographic imaging optics that resulted in ghost images.

Wednesday, May 2, 2:00 p.m., Parallel Session, Scotland

PROCESS INDUCED DAMAGE (Session 4C)

Co-Chairs: Terence Hook, IBM Microelectronics and Kin P. Cheung, Lucent Technologies

4C.1 THE IMPACT OF TRENCH GEOMETRY AND PROCESSING ON THE PERFORMANCE AND RELIABILITY OF LOW VOLTAGE POWER UMOSFETS—S.A. Suliman, N. Gallogunta, L. Trabzon, J. Hao*, G. Dolny*, R. Ridley*, T. Greb*, J. Benjamin*, C. Kocon*, J. Zeng*, O.O. Awadelkarim, S.J. Fonash, M. Horn, and J. Ruzyllo, Penn State Univ., University Park, PA

*Intersil, Mountaintop, PA

This paper reports on performance and reliability studies of vertical n-channel UMOSFETs. Using SEMs, charge pumping, and transistor parameter measurements, this study examines UMOSFET reliability in terms of trench geometry and trench processing. The effective mobility along the trench wall is shown to be a function of RIE-induced damage, and the reliability of the device to be strongly dependent on the depth and curvature of the trench.

4C.2 THE EFFECTS OF PLASMA INDUCED DAMAGE ON TRANSISTOR DEGRADATION AND THE RELATIONSHIP TO FIELD PROGRAMMABLE GATE ARRAY PERFORMANCE—F.E. Pagaduan, J.K. Lee, V. Vedagarbha, K. Lui, M.J. Hart, D. Gitlin, Xilinx, Inc., San Jose, CA, T. Takaso, S. Kamiyama, and K. Nakayama, Seiko Epson Corp., Yamagata-ken, Japan

This paper shows the effects of damage on a 4.5-nm gate oxide transistors and the resulting degradation observed on product-level performance of a Field Programmable Gate Array (FPGA). The magnitude of the PFET Negative Bias Temperature Instability is shown to be affected by a plasma ashing step. By eliminating this step the transistor degradation was reduced, and the product-level performance of the FPGA was also improved, correlating strongly with the measured transistor threshold shift.

4C.3 IMPROVEMENT OF MOSFET SUBTHRESHOLD LEAKAGE CURRENT BY ITS IRRADIATION WITH HYDROGEN RADICALS GENERATED IN MICROWAVE-EXCITED HIGH-DENSITY INERT GAS PLASMA—Y. Saito, H. Takahashi, K. Ohtsubo, M. Hirayama, S. Sugawa, Tohoku Univ., Aoba-ku, Japan, H. Aharoni, Ben-Gurion Univ., Beer-Sheva, Israel, and T. Ohmi, Tohoku Univ., Aoba-ku, Japan

In this paper it is shown that the drain leakage of MOSFETs is improved by irradiation with hydrogen radicals generated in a microwave-excited Ar/H₂ plasma. This specific conditions of the plasma were carefully chosen to produce a high flux of hydrogen radicals with minimal plasma-induced damage. Pressure, gas constituents, and the plasma generation technique were varied in these experiments to optimize the annealing effect without inducing damage.

Wednesday, May 2, 3:40 P.m., Parallel Session, Scotland

INTERCONNECT RELIABILITY (Session 4D)

Co-Chairs: Timothy Sullivan, IBM Microelectronics and James Walls, Motorola

4D.1 RESERVOIR MODELING FOR ELECTROMIGRATION IMPROVEMENT OF METAL SYSTEMS WITH REFRACTORY BARRIERS—M.J. Dion, Intersil, Melbourne, FL

Metal reservoirs have been shown to increase electromigration lifetimes in barrier metal systems. This study finds that EM lifetime increase is related to the log of reservoir length in a constant width line. Number of vias, via spacing, and metal overlap do not play significant roles in defining the EM lifetime.

4D.2 THE QUANTITATIVE ASSESSMENT OF STRESS-INDUCED VOIDING IN PROCESS QUALIFICATION—A. Fischer, A.E. Zitzelsberger, and M. Hommel, Infineon Technologies, Munchen, Germany

The primary stressmigration-related reliability risk is the resistanceincrease due to stress-induced voids. Based on experimental data, we present a new model for the estimation of the stressmigration-limited lifetime. Further, we show that reduced electromigration performance must be considered for stress-void damaged metal lines.

4D.3 STATISTICS OF ELECTROMIGRATION EARLY FAILURES IN CU/OXIDE DUAL-DAMASCENE INTERCONNECTS—E.T. Ogawa, K.-D. Lee, H. Matsuhashi, A.J. Bierwag, P.R. Justison, A.N. Ramamurthi, P.S. Ho, Univ. of TX at Austin, Austin, TX, V.A. Blaschke, and R.H. Havemann, SEMATECH, Austin, TX

Evidence of the statistical detection of two distinct ("weak" and "strong" mode) failures in dual-damascene Cu/oxide interconnects is reported. A combination of single and repeated serial chains of nominally identical interconnects are used in conjunction with statistical analysis based on "weakest-link" concepts. Results confirm the utility of the multi-link approach in electromigration reliability analysis.

4D.4 TRADE-OFF BETWEEN RELIABILITY AND POST-CMP DEFECTS WITH RECRYSTALLIZATION ANNEAL IN COPPER DAMASCENE INTERCONNECTS—G. Alers, Novellus Systems, San Jose, CA, D. Dornisch, Conexant, Newport Beach, CA, J. Siri, K. Kattige, L. Tam, E. Broadbent, and G. Ray, Novellus Systems, San Jose, CA

We have evaluated the impact of anneal on grain size, texture, stress, electromigration lifetime and density of post-CMP defects, such as pits and voids, in copper damascene interconnects. There appears to be a trade-off between full recrystallization of narrow trenches for improved electromigration lifetime and the occurrence of post-CMP defects which needs to be optimized.

4D.5 IMPACT OF LOW-K DIELECTRICS AND BARRIER METALS ON TDDB LIFETIME OF CU INTERCONNECTS—J. Noguchi, T. Saitoh, N. Ohashi, H. Ahihara, H. Maruyama, M. Kubo, and H. Yamaguchi, Hitachi, Ltd., Tokyo, Japan

TDDB characteristics of Cu interconnects using various low-k dielectrics and barrier metals were investigated. Degradation of TDDB due to Cu-ion diffusion is mainly caused, not by thermal stress, but by electrical stress. As the dielectric constant goes lower, the TDDB failure distributions a shifted to lower electric field strength.

Thursday, May 3, 8:00 a.m., Great Hall North

OXIDE II (Session 5)

Co-Chairs: Paul Nicollian, Texas Instruments and Robin Degraeve, IMEC

5.1 RELATION BETWEEN BREAKDOWN MODE AND BREAKDOWN LOCATION IN SHORT CHANNEL NMOSFETS AND ITS IMPACT ON RELIABILITY SPECIFICATIONS—R. Degraeve, B. Kaczer, A. De Keersgieter, and G. Groeseneken, IMEC, Leuven, Belgium

A method to determine the breakdown position in short channel nmosfets is introduced. We find that SBD occurs exclusively in the transistor channel while the hardest circuit killing breakdowns occur above the source and drain extension regions. Since these killing breakdowns make up only a small fraction of all breakdowns, a relaxation of the reliability specification is possible.

5.2 ANALYTIC MODELING OF LEAKAGE CURRENT THROUGH MULTIPLE BREAKDOWN PATHS IN SiO₂ FILMS—E. Miranda, Universidad de Buenos Aires, Buenos Aires, and J. Suñé, Universidad Autónoma de Barcelona, Bellaterra, Spain

An analytic model for the leakage current through broken down gate oxides in MOS structures is presented. It is based on the physics of mesoscopic conducting systems and the quantum properties of point contacts. The model covers the hard breakdown, the soft breakdown andthe stress-induced-leakage-current conduction modes in a consistent manner.

5.3 EXPERIMENTAL STUDY OF GATE VOLTAGE SCALING FOR TDDB UNDER DIRECT TUNNELING REGIME—M. Takayanagi, S. Takagi, and Y. Toyoshima, Toshiba Corp., Yokohama, Japan

The slope of Tbd with respect to V_g for TDDB is experimentally studied as a function of T_ox and V_g for accurate voltage scaling. A model to explain the experimental voltage acceleration factor is presented. It is quantitatively shown that the significant decrease in hole generation due to lower electron energy greatly helps the TDDB reliability at operating voltage.

5.4 ACCURATE AND ROBUST NOISE-BASED TRIGGER ALGORITHM FOR SOFT BREAKDOWN DETECTION IN ULTRA THIN OXIDES—P. Roussel, R. Degraeve, B. Kaczer, and G. Groeseneken, IMEC, Leuven, Belgium

An algorithm for accurate and robust triggering on soft breakdown during constant voltage stress based on gate current noise increase is presented. Triggering on current spikes or pre-BD events is avoided. This test assures correct SBD-detection in a wide range of stress conditions and various geometries.

5.5 SOFT BREAKDOWN TRIGGERS FOR LARGE AREA CAPACITORS UNDER CONSTANT VOLTAGE STRESS—J. Schmitz, H.J. Kretschmann, H.P. Tuinhout, and P.H. Woerlee, Philips Research Labs, Eindhoven, The Netherlands

This work discusses methods to identify a soft breakdown during constant voltage stress of large area capacitors (0.1-10 mm² ) with gate oxide thickness down to 1.8 nm. We show that with data filtering, the classical current increase trigger can still be used down to the thinnest oxide, while an increased RMS variation of the current does not identify all breakdowns.

Thursday, May 3, 10:30 a.m., Great Hall North

DISCUSSION PANEL (room TBD)

Is Burn-in Elimination Possible?

Panel:
Carl Peridier .......................... Agere Systems
Andy Forcier ......................... IBM Microelectronics
Bob Knoell ............................ Visteon
Bharapha Ragagopalan ......... Texas Instruments

Moderators:
William R. Tonti .......... IBM Microelectronics

Co-Chairs: Giuseppe La Rosa, IBM Microelectronics and RRoland Thewes, Infineon Technologies

6.1 ROLE OF E-E SCATTERING IN THE ENHANCEMENT OF CHANNEL HOT CARRIER DEGRADATION OF DEEP SUB-MICRON NMOSFETS AT HIGH V_GS CONDITIONS—S.E. Rauch III, G. La Rosa, and F. Guarin, IBM Microelectronics, Hopewell Jct., NY

We propose a new phenomenological CHC model, based on e-e scattering, that explains the worsening of the HC damage at high V_GS = V_DS observed in deep sub-micron NMOSFETs and allows HC lifetime predictions over the full gate voltage range. This description takes into account the dependence of the electron concentration near the drain on the applied V_GS and describes, for the first time, its impact to the EES induced HC damage.

6.2 ANALYSIS OF NEW HOT CARRIER DEGRADATION PHENOMENA: "W" OR "S" SHAPE EVOLUTION OF LDD NMOSFET—J.-R. Shih, L.H. Chu, R.Y. Shiue, and J. Yue, TSMC, Hsin-Chu, Taiwan

A new hot carrier phenomenon with "W" or "S"-shape evolution has been observed and analyzed. It does not follow the power law or the two-step degradation model. A three-stage degradation model has been proposed. The transistor with SSRW channel and LDD with 0°-tilt angle will enhance this effect.

6.3 ON THE DOMINANT INTERFACE TRAP GENERATION PROCESS DURING HOT-CARRIER STRESSING—S. Ang and C.H. Ling, The National Univ. of Singapore, Singapore

Analysis of a kink, observed in the charge pumping current versus time curve, supports a recent claim of a new interface trap generation process during hot-carrier stressing of MOSFETs. This process, which may be related to the interaction between hot carriers and the Si/SiO2 interface, exhibits a distinctively high generation coefficient, and could ultimately limit the lifetime of N-MOSFETs under ac operation.

6.4 A NEW PHYSICAL AND QUANTITATIVE WIDTH DEPENDENT HOT CARRIER MODEL FOR SHALLOW-TRENCH-ISOLATED CMOS DEVICES—S.S. Chung, S.-J. Chen, W.J. Yang, and J.-J. Yang, National Chiao Tung Univ., Hsinchu, Taiwan

Enhanced degradation in STI CMOS devices with reducing gate width was studied. A new physical and quantative model to describe the enhanced degradation for both n- and p-MOSFET's has been proposed. Results show that different mechanisms exist for either types of devices. The interface state is dominant for the n-MOSFET degradation, while the channel shortening induced oxide damage is dominant for p-MOSFET. Both are found to be related to the quality of the trench instead of the STI electric field.

6.5 HOT-CARRIER RELIABILITY OF p-MOSFET WITH ULTRA-THIN SILICON NITRIDE GATE DIELECTRIC—I. Polishchuk, Y.-C. Yeo, Q. Lu, T.-J. King, and C. Hu, Univ. of California, Berkeley, CA

Hot-carrier reliability of 0.1 µm p-MOSFET's with 14 Å T_{OX, EQ} silicon nitride gate dielectric was found to be similar to that of SiO₂ pMOSFET's. The device performance degradation is attributed to the interface traps created by hot holes.