ESSDERC´97

27th European Solid-State Device Research Conference
Stuttgart, 22-24 September 1997

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Overview
--> AM-LCDs bring solid-state devices to the display
van Ommen A., Philips Flat Panel Display Co.

Benchmarking Semiconductor Manufacturing
Hodges D.A., University of California

DRAM Technologies For Today`s Market And Future DRAM Generations
Neumueller W., Siemens AG

GaN based devices for electronic applications
Khan M.A., APA Optics Inc.

Human Capital for Growth in Microelectronics (The Brain Intensive Era)
Martinotti P., SGS Thomson Microelectronics

--> Metamorphics: extending the limits of GaAs
Salmer G., IEMN

Multi Layer Metallization
Lerme M., LETI CEA Grenoble

Multifunctional Intergration Using HEMT Technology
Schlechtweg et. al. M., Fraunhofer Institute

Noise analysis in devices under non-linear operation
Cappy A., IEMN

Optical litography, how far will it get us?
Van den hove L., IMEC

Prospects in Silicon Nanoelectronics
Van Rossum M., IMEC

--> Recent Progress with Vertical Transistors
Risch L., Siemens AG

RF Moblile Communication Circuits - Comparison of Technologies
Neuvo Y., Nokia Mobile Pones

--> Semiconductor Packaging and New Packaging Concepts
Beckenbaugh W.M., Adv. Interconnect Systems Labs

--> SiGe/Si-Heterostructure Devices - Status, Problems and Prospects
König U., Daimler Benz Research

Silicon Microsystems for Automotive Applications
Marek J., Robert Bosch GmbH

Silicon RF Technology - The Two Generic Approaches
Burghartz J., IBM

State of the Art in Compact Modelling with Emphasis on Bipolar RF Circuit Design
de Graaff H.C., Delft University of Technology

Stategic Alliances for highly efficient 300 mm Waferfabs
Gießmann J., Meissner & Wurst GmbH+Co

Statisitcal Analysis for IC-Management
Kibarian J. K., PDF Solutions

The transistor´s discovery and what´s ahead
Pinto M.R., Lucent Technologies

--> Tunneling gate oxide MOSFET technology
Momose H.S., Toshiba Corp.

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Compound Semiconductor Devices and Technology 18 GHz high gain monolithically integrated InP/InGaAs PIN/HBT-Receiver
Huber D., Swiss Federal Inst. of Technology

A fully GaAs-based 100MHz, 2W DC-to-DC Power Converter
Ajram S., IEMN-DHS

A Novel Functional Heterostructure-Emitter and Hereostructure-Base Transistor (HEHBT)
Liu W.-C., National Cheng-Kung University

An InP-HBT technology for monolithic optoelectronic receivers with 24 GHz bandwidth
Willén B., Royal Institute of Technology

Analysis of electron spreadinge effects in pixelless quantum well imaging devices
Ryzhii V., The University of Aizu

--> Analytical modeling of InP/InGaAs HBTs
Rezazadeh A., King's College London

GaAs Schottky Gate bipolar transistors for high voltage power switching applications
Johnson C. M., University of Newcastle

High Frequency Analysis of InP Transistors versus Temperature
Aniel F., University Paris-South

High-Frequency Small-Signal and Large-Signal Characteristics of Resonant Tunneling High Electron Mobility Transistors
Chen K.J., City University of Hong Kong

Microplasma and Uniform Gate Breakdown in MESFETs
Vashchenko V.A., State Research Institute "Pulsar"

--> Novel Fabrication Technology for Ultra-Compact Three-Dimensional MMICs
Sugitani S., NTT Systems Electronics Labs.

Parasitic bipolar effects leading to on-state breakdown in 2D-MESFETs
Meneghesso G., Università di Padova

--> Polyimide Optical Waveguide with Multi-Fan-Out for Multichip Module Application
Matsumoto T., Tohoku University

Reexamination of Electron Mobility Dependence on Dopants in GaAs
Köpf Ch., TU Vienna

Transferred Electron Effect in AlGaAs/GaAs Multi-Quantum-Well Structures
Springer A.L., University of Linz

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Packaging and Reliability A Stress Technique Suitable For The In-Line Reliability Monitoring Of The Hot Carrier Endurance of Sub-0,5um MOSFETs
Dimitriadis C., NCSR "DEMOCRITOS"

Building in reliability with latch-up, ESD and hot carrier effects on a 0.25 µm CMOS technology
Leroux C., LETI/CEA, Grenoble

Comparative hot carrier induced degradation in 0,25 µm MOSFETs with H or D passivated interfaces
Autran J.L., INSA de Lyon

Correlation between electromigration damage kinetics and microstructure in Cu interconnects
Karpovski M., Tel Aviv University

Effects of high temperature on performances and hot-carrier reliability in DC/AC stressed 0.35 µm n-MOSFETs
Bravaix A., ISEM Toulon

Electro-Thermal Interaction on Circuit Level under the Influence of Packaging
Digele G., Robert Bosch GmbH

--> Enhanced hot-carrier induced degradation in STI isolated NMOS transistors
Sallagoity P., SGS-Thomson Microelectronics

Finite Element Analysis of Stress Distributions in Interconnect Structures
Coughlan J., Nat. Microelectronics Research Centre

HBM and CDM ESD stress test results in 0.6 µm CMOS structures
Meneghesso G., Università di Padova

Hot Carrier effects and time-dependent degradation laws in 0.1µm bulk Si n-MOSFETs
Marchand B., LPCS, ENSERG, Grenoble

Influence of thermal heating effect on pulsed DC electromigration result analysis
Waltz P., LETI/CEA, Grenoble

On the determination of the time-dependent degradation laws in deep submicron SOI MOSFETs
Renn S.H., LPCS, ENSERG, Grenoble

Stress induced leakage current dependence on oxide thickness, technology and stress level
Scarpa A., Università di Padova

Two-stage degradation of submicron LDD n-MOSFETs by 1/f noise, charge pumping, and drain current measurements
Okhonin S., Swiss Federal Institute of Technology

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Process and Device Modelling A Consistent Parameter Extraction Method for Deep Submicron MOSFETs
Klein P., Siemens AG

--> A new cellular etching-simulator for InP and Si
Wehmann H.-H., Technische Universität Braunschweig

A New Method for Verification of MOSFET Models Based on Device Parameter Variations
Kühn C., Universität der Bundeswehr

A new numerical method for determining the excess noise power spectrum in MOSFETs
Longoni A., Politecnico di Milano

--> A Novel Diffusion Coupled Oxidation Model
Radi M., TU Vienna

A Physically Based Substrate Current Simulation
Knaipp M., TU Vienna

A Unified Approach for Modeling Multiterminal Bipolar and MOS Devices in Smart-Power Technologies
Speciale N., University of Bologna

--> Analysis of Capacitance Behavior for Short-Channel Accumulation-Mode SOI PMOS Devices
Kuo J.B., National Taiwan University

Circuit simulation through coordinated EM and solid-state device numerical analyses
Ciampolini P., Università di Perugia

--> Closed-form model of the subhalfmicrometer LDD MOSFET overlap capacitance
Kol´dyaev V.I., IMEC

Comparison of an L-array and a single transistor method to extract Leff and Rs in deep submicron MOSFETs
Biesemans S., IMEC

Cost effective simulation of three-dimensional effects in the shallow trench isolation process
Poncet A., France Telecom - CNET

Determination of interface state density of ULSI n-MOSFET by 1/f noise measurements
Villa S., Politecnico di Milano

Efficient Parameter Extraction and Statistical Analysis for a 0.25µm low-power CMOS Process
Saavedra Diaz E.V., National Microelectronics Research Centre

Electrical modelling of Kelvin structures for the derivation of low specific contact resistivity
Reeves G.K., Royal Melbourne Inst. of Technology

Examination of theTransient Drift-Diffusion and Hydrodynamic Modeling Accuracy for SiGe HBTs by 2D Monte-Carlo Device Simulation
Neinhüs B., University of Bremen

Full Band Monte-Carlo Device Simulation of an 0.1 µm N-Channel MOSFET in Strained Silicon Material
Keith S., Universität Bremen

Hot carrier effect in sub-0.1µm SOI-MOSFETs
Rauly E., LPCS, ENSERG, Grenoble

Impact of non-equilibrium transport and series resistances in 0.1µm bulk and SOI MOSFETs
Bricout P.H., Inst. Supérieur d'Electronique Nord

Influence of Excitonic Scattering on Charge Carrier Ambipolar Diffusion in Silicon
Velmre E., Tallinn Technical University

Influence of substrate type on interconnect peformance
Delorme N., LETI/CEA, Grenoble

Investigation of the influence of impact ionization feedback on the spatial distribution of hot carriers in an NMOSFET
Jungemann C., University of Bremen

MAIDS: A Microwave Active Integral Device Simulator
de Vreede L.C.N., Delft University of Technology

--> Measurement of Channel Length and Off-set Region Length for Off-set Gate MOSFETs
Terada K., Hiroshima City University

Monte Carlo comparative study of current-mode noise in Si/Si 1-x Ge x Strained Heterojunctions
Velásquez J.E, Universidad de Salamanca

Monte Carlo study on electron transport properties in double-gate fully depleted SOI-MOSFETs
Gámiz F., Universidad de Granada

New parameter extraction method for the simulation of the space charge created by Fowler-Nordheim electron injections in the gate oxide of MOS devices
Auriel G., ENSPM

Optimization of a Lateral DMOS Transistor for Low Voltage, RF Power Operation
van Melick N.G.H., Eindhoven University of Technology

Performance limits of deep submicron buried channel delta doped MOSFETs
O`Neil A.G., University of Newcastle

Predictive expression of propagation delay in short channel CMOS/SOI inverter using Monte Carlo simulation
Arbey M.E., Université Paris XI

Rapid IC Performance Yield and distribution prediction using a rotation of the circuit parameter principals components
Horan J., Cork Regional Technical College

RF performance of strained Si MODFETs and MOSFETs on "virtual" SiGe substrates: A Monte Carlo study
Asenov A., University of Glasgow

Selectively-Implanted Collector Profile Optimisation for High-Speed Vertical Bipolar Transistors
Peter M.S., Philips Research Laboratories

Simulation of avalanche injection filamentation in MOSFET's and IGBT's
Vashchenko V.A., State Research Institute "Pulsar"

Studies on the heat removal features of stacked SOI structures with a dedicated field solver program (SUNRED)
Kohári Zs., Technical University of Budapest

Theoretical Analysis of a Pseudo-Floating Gate flash EEPROM Device
Concannon A., Nat. Microelectron. Res. Cent. Cork

Theory and modelling of organic field effect transistors
Scheinert S., Technische Universität Ilmenau

Thermal analytical model for analysis of pulsed DC electromigration results
Waltz P., LETI/CEA, Grenoble

Thermal resistance modelling of RF high power bipolar transistors
Mouthaan K., Delft University of Technology

Three-Dimensional Simulation of Contact Hole Metallization using Aluminum Sputter Deposition at Elevated Temperatures
Bär E., Universität Erlangen-Nürnberg

Two-dimensional analytical model of subthreshold current in fully-depleted SOI MOSFETs
Pidin S., Tohoku University

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Sensors, Actuators and Displays A 73 GHz SiGe SIMMWIC module
Strohm K.M., Daimler Benz AG

--> A new structure for reduction of the leakage currrent in the low temperature Poly-Si TFTs fabricated by the MILC process
Ihn T.-H., Seoul National University

A novel gas sensor for hydrocarbons detection based on porous silicon permeated with Sn-V mixed oxides
Angelucci R., CNR LAMEL - Institute

A Reflective-mode PDLC Light Valve Display Technology
Cacharelis Ph., National Semiconductor Cor.

Al-n-Si Double-Schottky Photodiodes for Optical Storage Systems
Seto M, Philips Research Laboratories

An alternative method to monitor and control the IC temperature in the 4.2-77 K range
Gutiérrez-D. E. A,, INAOE

Enhancement of TFT Performance by Low Temperature Oxygen Annealing
Quinn L.J., Northern Ireland Semicon. Res. Cen.

Gate bias aging of unhydrogenated polycrystalline silicon TFTs
Mohammed-Brahim T., Site Universitaire

Integrated array of avalanche photodiodes for single-photon counting
Zappa F., Politecnico di Milano

--> New Designs, Readout Concept and Simulation Approach of Micromachined Rate Gyroscopes
Geiger W., HSG-IMIT

--> Piezoresistive bridge configuration for atomic force microscopy
Jumpertz R., Forschungszentrum Jülich

Slot-antenna-coupled microbolometers for far-infrared detection
Yasuoka Y., National Defense Academy

Vibration sensor with optoelectronic interface
Peiner E., Technische Universität Braunschweig

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Silicon Devices A 9 GHz Bandwith Preamplifier in 10 Gbps Optical Receiver Using SiGe Base HBT
Ryum B.R., Electronics and Telecom. Research Institute

A comparative study of three designs of 0.10 µm NMOSFETs processed with heavy ion implanted pocket
Guegan G., LETI/CEA, Grenoble

A high voltage nDMOS structure in a standard sub-micron CMOS process
Vermandel M., Universiteit Gent

A Study of Temperature Distribution in SOI-Smart Power Devices in Transient Conditions by Optical Interferometry
Seliger N., TU Vienna

Advanced self aligned SOI concepts for vertical MOS transistors with ultrashort channel lengths
Aeugle Th., Siemens AG

Control of steep Boron profiles in Si/SiGe heterojunction bipolar transistors
Heinemann B., Institute for Semiconductor Physics

Detailed Matching Analysis of Sub-50 nm-MOS-Transistors
Horstmann J.T., University of Dortmund

Development of the Next Generation of Insulated Gate Bipolar Tranistors based on Trench Technology
Udrea F., University of Cambridge

Dynamic floating body effects in PD SOI MOSFETs biased in the kink region
Perron L., Politecnico di Milano

Effects of processing temperatures on device design rules for Silicon/Silicon Germanium heterojunction bipolar transistors
Bashir R., National Semiconductor Cor.

Fabrication of 0.1 µ m MOSFET with Super Self-Aligned Ultrashallow Junction Electrodes Using Selective Si1-x Gex CVD
Murota J., Tohoku University

Flexible Micro-Photodiode Array as a Subretinal Implant
Schubert M.B., University of Stuttgart

Inverse SiGe Heterojunction Bipolar Transistor
van den Oever L.C.M., Delft University of Technology

Investigations on the Internal Physical Behaviour of 600V Punch-Through IGBT under Latch-up at High Temperature
Azzopardi S., Université de Bordeaux I

Lateral Channel Doping Engineering in 0.1µm Recessed Channel nMOSFETs
Lyu J., Seoul National University

Limitations of Double Polysilicon Self-Aligned Bipolar Transistor Structure
Inoh K., Toshiba Corporation

Low frequency 1/f noise characterization of advanced CMOS-compatible bipolar junction transistors for technology evaluation
Chroboczek J.A., France Telecom - CNET

Low-Frequency Noise Characteristics of Advanced Si and SiGe Bipolar Transistors
Gabl R., Siemens AG

Low-Noise Amplifier for Mobile Communications using a Production Ready SiGe HBT Technology
Erben U., University of Ulm

New anti-punchthrough design for buried channel PMOSFET
Son J., LG Semicon Co., Ltd.

Noise performances and hot carrier efects in polysilicon thin film transistors
Mariucci L., IESS-CNR

On the transconductance enhancement at low temperature in deep submicron MOSFETs
Szelag B., ENSERG Grenoble

Optical testing of submicron-technology MOSFETs and bipolar transistors
Pogany D., TU Vienna

Periodic Transconductance Oscillations in Sub-100nm MOSFETs
Wirth G., Fed. University of Rio Grande do Sul

--> Realisation of a 0.1 µm vertical MOSFET with a SiGe source
Hall S., The University of Liverpool

Realization and Evaluation of an Ultra Low-Voltage/Low-Power 0.25µm (n+/p+) Dual-Workfunction CMOS Technology
Schwalke U., Siemens AG

--> RTS diagnostics of source-drain (edge?) related defects in submicron n-MOSFETs
Simoen E., IMEC

SiGe gate for highly performant 0.15/0.18µm CMOS technology
Skotnicki T., France Telecom - CNET

Source/Drain Engineering with Ge Large Angle Tilt Implantation and Pre-Amorphization to Improve Currrent Drive and Alleviate Floating Body Effects of Thin Film SOI MOSFETs
Woo J.C.S., University of California

Study of pocket implant parameters for 0,18 µm CMOS
Schmitz J., Philips Research Laboratories

Suppression of the Reverse Short Channel Effect in (Sub-)0.25µm nMOSFETs using elevated S/D structures
Schumann D., Siemens AG

Temperature dependence (300-600K) of parasitic bipolar effects in SOI-MOSFETs
Reichert G., ENSERG Grenoble

The Design and Characterisation of a SiGe I²L Technology
Moiseiwitsch N.E., University of Southampton

The Planar-Doped-Barrier-FET: MOSFET Overcomes Conventional Limitations
Hansch W., Universität der Bundeswehr München

Voltage controlled colour separation in two-terminal a-Si:H based sensor structures
Neidlinger Th., University of Stuttgart

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Silicon IC Technology 0.25 µm NMOS transistor with nitride spacer: reduction of the short channel effect by optimisation of the gate reoxidation process and reliablity
Ada-Hanifi M., SGS-Thomson Microelectronics

A 0.5 µm Flash Technology suitable for Low Voltage Embedded Applications
Yeh J.K., Taiwan Semiconductor Manufacturing

A 34 GHz fT Bipolar Process with High-Energy-Implanted Collector
Ponomarev Y.V., Philips Research Laboratories

A cost effective smart power technology for 45V applications
Marty-Blavier A., Motorola

A High Performance 0.18 µm CMOS Technology Designed for Manufacturability
Badenes G., IMEC

--> A Manufacturable 0.35 µm BiCMOS using Self-Aligned Cobalt SilicideTechnology
Igarashi T., Mitsubishi Electric Corporation

A performance comparison between 0.35µm self-aligned and quasi-self-aligned double-polysilicon bipolar transistors
Ailloud L., SGS Thomson Microelectronics

--> An Improved Technology for Elevated Source/Drain MOSFETS
Waite A.M., University of Southampton

An investigation of polysilicon emitter bipolar transistors with an ozonized polysilicon/monosilicon interface
Niel S., France Telecom - CNET

As and B Diffusion in TiSi2/Polysilicon Gates with Dual Workfunction Gate Technology
Berthold A., Siemens AG

C-V characteristics of Pt/SrBi2Ta2O9/CeO2/Si structure for non-volatile memory devices
Kim Y.T., Korea Inst. of Science and Technol.

CMOS Production Compatible SiGe Heteroepitaxy for High Frequency Circuits
Ritter G., Institute for Semiconductor Physics

--> Enhanced Breakdown Voltage and Charge to Breakdown of Collector Implant-Gate Oxide-Poly Capacitors by Selective Epitaxial Growth
Leipold D., Texas Instruments Gmbh Germany

Influence of CMOS-circuit areas on RF-damping of gold and aluminium microstripline in combined SIMMWIC-CMOS technology
Beck D., University of Stuttgart

Investigation of the effect of the extension implant energy on deep submicron CMOS device performance
Kubicek S., IMEC

Junctions design guidelines for 0.18µm CMOS
Gwoziecki R., France Telecom - CNET

Laser induced reversible change of electrical resistivity of CoSi2 thin film
Knite M., Riga Technical University

Low-Cost CMOS Process with Complete Post-Gate Implantation Scheme
Kerber M., Siemens AG

--> Mechanisms of Localized Charge Injection: A Technique to Characterize Gate Edge Damage in MOS Transistors
Viswanathan C.R., University of California

Nanometer Scale Lithography of Silicon and Titanium using Scanning Probe Microscopy
Dubois E., IEMN/ISEN

Optimisation of Ultra High Density MOS Arrays in 3D
Haneder T., University of Regensburg

--> Patterning of Pt/RuO2 electrodes for Pb(Zr,Ti)O3 in an Inductively Coupled Cl2/O2 Plasma
Park S.-G., Inha University

Self-aligned metallization of high-frequency BJT´s with low-stress silicon-nitride spacers
van Zeijl H.W., Delft University of Technology

Surface recombination velocity measurement in SPEG SOS MOSFETs by bipolar gain characterisation
Stevens P. B., Middlesex University

Technology of the Diode Programmable Read Only Memory
Lifka H., Philips Research Laboratories

The impact of the S/D extensions on the drain current characteristics of deep submicron Si nMOSFETs at 77 K
Simoen E., IMEC

--> The Oxidized Amorphous Silicon Improved LOCal Isolation (OASI-LOCI) concept
Deleonibus S., LETI/CEA, Grenoble

Thinning Oxide-Nitride-Oxide Interpoly Dielectric (11-13nm) for 0.25 µm Flash Cell Memories
Candelier P., LETI/CEA, Grenoble

Two-Step Deposition Method for Improvement of the Electrical Characteristics of BST Thin Films
Kil D.-S., Seoul National University