| Index |
Cost effective simulation of three-dimensional effects in the shallow trench isolation process Ada-Hanifi M., SGS-Thomson Microelectronics 0.25 µm NMOS transistor with nitride spacer: reduction of the short channel effect by optimisation of the gate reoxidation process and reliablity Adde R., University Paris-South High Frequency Analysis of InP Transistors versus Temperature Aeugle Th., Siemens AG Advanced self aligned SOI concepts for vertical MOS transistors with ultrashort channel lengths Aeugle T., Siemens AG --> Recent Progress with Vertical Transistors Ailloud L., SGS Thomson Microelectronics A performance comparison between 0.35µm self-aligned and quasi-self-aligned double-polysilicon bipolar transistors Ajram S., IEMN-DHS A fully GaAs-based 100MHz, 2W DC-to-DC Power Converter Alieu J., France Telecom - CNET, Meylan, France --> Enhanced hot-carrier induced degradation in STI isolated NMOS transistors Almeyda A., University Paris-South High Frequency Analysis of InP Transistors versus Temperature Alsmeier J., Siemens AG DRAM Technologies For Today`s Market And Future DRAM Generations Amaratunga G.A.J., Liverpool University, UK Development of the Next Generation of Insulated Gate Bipolar Tranistors based on Trench Technology Angelucci R., CNR LAMEL - Institute A novel gas sensor for hydrocarbons detection based on porous silicon permeated with Sn-V mixed oxides Aniel F., University Paris-South High Frequency Analysis of InP Transistors versus Temperature Aoyama S., NTT Systems Electronics Labs. --> Novel Fabrication Technology for Ultra-Compact Three-Dimensional MMICs Arbey M.E., Université Paris XI Predictive expression of propagation delay in short channel CMOS/SOI inverter using Monte Carlo simulation Armstrong B.M., Northern Ireland Semicon. Res. Cen. Enhancement of TFT Performance by Low Temperature Oxygen Annealing Arnaud L., LETI/CEA, Grenoble Influence of thermal heating effect on pulsed DC electromigration result analysis Thermal analytical model for analysis of pulsed DC electromigration results Arno A., Delft University of Technology Thermal resistance modelling of RF high power bipolar transistors Asai S., Mitsubishi Electric Corporation --> A Manufacturable 0.35 µm BiCMOS using Self-Aligned Cobalt SilicideTechnology Asenov A., University of Glasgow RF performance of strained Si MODFETs and MOSFETs on "virtual" SiGe substrates: A Monte Carlo study Ashburn P., University of Southampton The Design and Characterisation of a SiGe I²L Technology Aufinger K., Siemens AG Low-Frequency Noise Characteristics of Advanced Si and SiGe Bipolar Transistors Augendre E., LETI/CEA, Grenoble, France Impact of non-equilibrium transport and series resistances in 0.1µm bulk and SOI MOSFETs Auriel G., ENSPM New parameter extraction method for the simulation of the space charge created by Fowler-Nordheim electron injections in the gate oxide of MOS devices Autran J.L., INSA de Lyon Comparative hot carrier induced degradation in 0,25 µm MOSFETs with H or D passivated interfaces Auvert G., France Telecom - CNET A performance comparison between 0.35µm self-aligned and quasi-self-aligned double-polysilicon bipolar transistors Azzopardi S., Université de Bordeaux I Investigations on the Internal Physical Behaviour of 600V Punch-Through IGBT under Latch-up at High Temperature B RF performance of strained Si MODFETs and MOSFETs on "virtual" SiGe substrates: A Monte Carlo study Badenes G., IMEC A High Performance 0.18 µm CMOS Technology Designed for Manufacturability Baine P.T., Northern Ireland Semicon. Res. Cen. Enhancement of TFT Performance by Low Temperature Oxygen Annealing Balestra F., ENSERG Grenoble On the transconductance enhancement at low temperature in deep submicron MOSFETs Temperature dependence (300-600K) of parasitic bipolar effects in SOI-MOSFETs Balestra F., LPCS, ENSERG, Grenoble On the determination of the time-dependent degradation laws in deep submicron SOI MOSFETs Hot carrier effect in sub-0.1µm SOI-MOSFETs Hot Carrier effects and time-dependent degradation laws in 0.1µm bulk Si n-MOSFETs Bär E., Universität Erlangen-Nürnberg Three-Dimensional Simulation of Contact Hole Metallization using Aluminum Sputter Deposition at Elevated Temperatures Barker J.R., University of Glasgow RF performance of strained Si MODFETs and MOSFETs on "virtual" SiGe substrates: A Monte Carlo study Barloti Y., Riga Technical University Laser induced reversible change of electrical resistivity of CoSi2 thin film Bartoletti G., France Telecom - CNET A performance comparison between 0.35µm self-aligned and quasi-self-aligned double-polysilicon bipolar transistors Bashir R., National Semiconductor Cor. Effects of processing temperatures on device design rules for Silicon/Silicon Germanium heterojunction bipolar transistors Basso M.T., SGS-Thomson Microelectronics 0.25 µm NMOS transistor with nitride spacer: reduction of the short channel effect by optimisation of the gate reoxidation process and reliablity Bauknecht R., Swiss Federal Inst. of Technology 18 GHz high gain monolithically integrated InP/InGaAs PIN/HBT-Receiver Beaumont S.P., University of Glasgow RF performance of strained Si MODFETs and MOSFETs on "virtual" SiGe substrates: A Monte Carlo study Beck D., University of Stuttgart Influence of CMOS-circuit areas on RF-damping of gold and aluminium microstripline in combined SIMMWIC-CMOS technology Beckenbaugh W.M., Adv. Interconnect Systems Labs --> Semiconductor Packaging and New Packaging Concepts Behammer D., Daimler Benz AG, Ulm, Germany Advanced self aligned SOI concepts for vertical MOS transistors with ultrashort channel lengths Beisswanger F., Temic Telefunken Microelectronic, Heilbronn, Germany A 73 GHz SiGe SIMMWIC module Belleville M., LETI/CEA, Grenoble Influence of substrate type on interconnect peformance Berenguer M., France Telecom - CNET An investigation of polysilicon emitter bipolar transistors with an ozonized polysilicon/monosilicon interface Bergamaschi C., Swiss Federal Inst. of Technology 18 GHz high gain monolithically integrated InP/InGaAs PIN/HBT-Receiver Bertagnolli E., Siemens AG, Munich, Germany Optimisation of Ultra High Density MOS Arrays in 3D Berthold J., Siemens AG Realization and Evaluation of an Ultra Low-Voltage/Low-Power 0.25µm (n+/p+) Dual-Workfunction CMOS Technology Berthold A., Siemens AG As and B Diffusion in TiSi2/Polysilicon Gates with Dual Workfunction Gate Technology Biesemans S., IMEC Investigation of the effect of the extension implant energy on deep submicron CMOS device performance The impact of the S/D extensions on the drain current characteristics of deep submicron Si nMOSFETs at 77 K Comparison of an L-array and a single transistor method to extract Leff and Rs in deep submicron MOSFETs Bitter M., Swiss Federal Inst. of Technology 18 GHz high gain monolithically integrated InP/InGaAs PIN/HBT-Receiver Blachier D., LETI/CEA, Grenoble Building in reliability with latch-up, ESD and hot carrier effects on a 0.25 µm CMOS technology Blanc G., Motorola A cost effective smart power technology for 45V applications Böck J., Siemens AG Low-Frequency Noise Characteristics of Advanced Si and SiGe Bipolar Transistors Boehm T., Siemens AG, Munich, Germany Optimisation of Ultra High Density MOS Arrays in 3D Boivin P., SGS-Thomson Microelectronics, Rousset, France New parameter extraction method for the simulation of the space charge created by Fowler-Nordheim electron injections in the gate oxide of MOS devices Bolze D., Institute for Semiconductor Physics CMOS Production Compatible SiGe Heteroepitaxy for High Frequency Circuits Bonis M, CNET - CNS, Meylan, France Building in reliability with latch-up, ESD and hot carrier effects on a 0.25 µm CMOS technology Bonis M., SGS-Thomson Microelectronics 0.25 µm NMOS transistor with nitride spacer: reduction of the short channel effect by optimisation of the gate reoxidation process and reliablity Bonnaud O., Université de Rennes I Gate bias aging of unhydrogenated polycrystalline silicon TFTs Bouillon P., France Telecom - CNET Junctions design guidelines for 0.18µm CMOS SiGe gate for highly performant 0.15/0.18µm CMOS technology Bourenkov A., Fraunhofer-Institut, Erlangen, Germany Realization and Evaluation of an Ultra Low-Voltage/Low-Power 0.25µm (n+/p+) Dual-Workfunction CMOS Technology Bracken C., National Semiconductor Cor. Effects of processing temperatures on device design rules for Silicon/Silicon Germanium heterojunction bipolar transistors Brambilla M., SGS-Thomson Microelectronics, Agrate Brianza,Italy HBM and CDM ESD stress test results in 0.6 µm CMOS structures Bravaix A., ISEM Toulon Effects of high temperature on performances and hot-carrier reliability in DC/AC stressed 0.35 µm n-MOSFETs Bricout P.H., Inst. Supérieur d'Electronique Nord Impact of non-equilibrium transport and series resistances in 0.1µm bulk and SOI MOSFETs Brini J., LPCS/ENSERG, Grenoble, France Stress induced leakage current dependence on oxide thickness, technology and stress level Brinkman W.F., Lucent Technologies The transistor´s discovery and what´s ahead Bronner G., IBM DRAM Technologies For Today`s Market And Future DRAM Generations Brozek T., Motorola, Austin, United States --> Mechanisms of Localized Charge Injection: A Technique to Characterize Gate Edge Damage in MOS Transistors Brüggemann R., University of Stuttgart Voltage controlled colour separation in two-terminal a-Si:H based sensor structures Brummack H., University of Stuttgart Voltage controlled colour separation in two-terminal a-Si:H based sensor structures Bufler F.M., Universität Bremen Full Band Monte-Carlo Device Simulation of an 0.1 µm N-Channel MOSFET in Strained Silicon Material Buonincontri S., Università di Perugia Circuit simulation through coordinated EM and solid-state device numerical analyses Burghartz J., IBM Silicon RF Technology - The Two Generic Approaches C A Reflective-mode PDLC Light Valve Display Technology Caillat C., LETI/CEA, Grenoble A comparative study of three designs of 0.10 µm NMOSFETs processed with heavy ion implanted pocket Canali C., Università di Modena, Italy Parasitic bipolar effects leading to on-state breakdown in 2D-MESFETs Candelier P., LETI/CEA, Grenoble Thinning Oxide-Nitride-Oxide Interpoly Dielectric (11-13nm) for 0.25 µm Flash Cell Memories Cappy A., IEMN Noise analysis in devices under non-linear operation Carceller J.E., Universidad de Granada Monte Carlo study on electron transport properties in double-gate fully depleted SOI-MOSFETs Cardinali G.C., CNR LAMEL - Institute A novel gas sensor for hydrocarbons detection based on porous silicon permeated with Sn-V mixed oxides Carluccio R., IESS-CNR Noise performances and hot carrier efects in polysilicon thin film transistors Cavani F., Dip. di Chimica Indust. e dei Materiali A novel gas sensor for hydrocarbons detection based on porous silicon permeated with Sn-V mixed oxides Caymax M., IMEC, Leuven, Belgium --> An Improved Technology for Elevated Source/Drain MOSFETS Chahoud M., Technische Universität Braunschweig --> A new cellular etching-simulator for InP and Si Chan S.S.M., GEC Plessey Semiconductors, Lincoln, UK Development of the Next Generation of Insulated Gate Bipolar Tranistors based on Trench Technology Chantre A., France Telecom - CNET A performance comparison between 0.35µm self-aligned and quasi-self-aligned double-polysilicon bipolar transistors An investigation of polysilicon emitter bipolar transistors with an ozonized polysilicon/monosilicon interface Chen J.-Y., National Cheng-Kung University A Novel Functional Heterostructure-Emitter and Hereostructure-Base Transistor (HEHBT) Chen K., Philips Semiconductors, Eindhoven, Netherlands A 0.5 µm Flash Technology suitable for Low Voltage Embedded Applications Chen M., Philips Semiconductors, Eindhoven, Netherlands A 0.5 µm Flash Technology suitable for Low Voltage Embedded Applications Chen K.J., City University of Hong Kong High-Frequency Small-Signal and Large-Signal Characteristics of Resonant Tunneling High Electron Mobility Transistors Cheng S.-Y., National Cheng-Kung University A Novel Functional Heterostructure-Emitter and Hereostructure-Base Transistor (HEHBT) Chilo J., PFT - CEM, Saint Martin d´Hères, France Influence of substrate type on interconnect peformance Cho D.-H., Electronics and Telecom. Res. Inst. A 9 GHz Bandwith Preamplifier in 10 Gbps Optical Receiver Using SiGe Base HBT Choh S.H., Korea University C-V characteristics of Pt/SrBi2Ta2O9/CeO2/Si structure for non-volatile memory devices Choi D.-K., Hanyang University, Seoul, Korea --> Patterning of Pt/RuO2 electrodes for Pb(Zr,Ti)O3 in an Inductively Coupled Cl2/O2 Plasma Choi Y., Seoul National University Lateral Channel Doping Engineering in 0.1µm Recessed Channel nMOSFETs Chroboczek J.A., France Telecom - CNET Low frequency 1/f noise characterization of advanced CMOS-compatible bipolar junction transistors for technology evaluation Chun K., Seoul National University Lateral Channel Doping Engineering in 0.1µm Recessed Channel nMOSFETs Ciampolini P., Università di Perugia Circuit simulation through coordinated EM and solid-state device numerical analyses Claeys C., IMEC --> RTS diagnostics of source-drain (edge?) related defects in submicron n-MOSFETs The impact of the S/D extensions on the drain current characteristics of deep submicron Si nMOSFETs at 77 K Colclaser R., Philips Semiconductors, Eindhoven, Netherlands A 0.5 µm Flash Technology suitable for Low Voltage Embedded Applications Colombo P., SGS-Thomson Microelectronics, Agrate Brianza,Italy HBM and CDM ESD stress test results in 0.6 µm CMOS structures Concannon A., Nat. Microelectron. Res. Cent. Cork Theoretical Analysis of a Pseudo-Floating Gate flash EEPROM Device Conncanon A., NMRC, Cork, Ireland A Stress Technique Suitable For The In-Line Reliability Monitoring Of The Hot Carrier Endurance of Sub-0,5um MOSFETs Cordier Y., IEMN, Villeneuved'Ascq --> Metamorphics: extending the limits of GaAs Coughlan J., Nat. Microelectronics Research Centre Finite Element Analysis of Stress Distributions in Interconnect Structures Cova S., Politecnico di Milano Integrated array of avalanche photodiodes for single-photon counting Crees D.E., GEC Plessey Semiconductors, Lincoln, UK Development of the Next Generation of Insulated Gate Bipolar Tranistors based on Trench Technology Cristiloveanu S., ENSERG Grenoble Temperature dependence (300-600K) of parasitic bipolar effects in SOI-MOSFETs Critelli C., Dip. di Chimica Indust. e dei Materiali A novel gas sensor for hydrocarbons detection based on porous silicon permeated with Sn-V mixed oxides Crozat P., University Paris-South High Frequency Analysis of InP Transistors versus Temperature D A comparative study of three designs of 0.10 µm NMOSFETs processed with heavy ion implanted pocket Dambrine G., IEMN Noise analysis in devices under non-linear operation Danelon V., University Paris-South High Frequency Analysis of InP Transistors versus Temperature Danneville F., IEMN Noise analysis in devices under non-linear operation De Backere C., Universiteit Gent A high voltage nDMOS structure in a standard sub-micron CMOS process De Geronimo G., Politecnico di Milano Determination of interface state density of ULSI n-MOSFET by 1/f noise measurements A new numerical method for determining the excess noise power spectrum in MOSFETs de Graaf C., Philips Research Laboratories Technology of the Diode Programmable Read Only Memory de Graaff H.C., Delft University of Technology MAIDS: A Microwave Active Integral Device Simulator Thermal resistance modelling of RF high power bipolar transistors State of the Art in Compact Modelling with Emphasis on Bipolar RF Circuit Design De la Hidalga-W. J., INAOE An alternative method to monitor and control the IC temperature in the 4.2-77 K range De Meyer K., IMEC Investigation of the effect of the extension implant energy on deep submicron CMOS device performance The impact of the S/D extensions on the drain current characteristics of deep submicron Si nMOSFETs at 77 K Comparison of an L-array and a single transistor method to extract Leff and Rs in deep submicron MOSFETs de Pontcharra J., CEA-LETI, Grenoble, France A performance comparison between 0.35µm self-aligned and quasi-self-aligned double-polysilicon bipolar transistors De Salvo B., LPCS, ENSERG, Grenoble, France Thinning Oxide-Nitride-Oxide Interpoly Dielectric (11-13nm) for 0.25 µm Flash Cell Memories de Vreede P.W.H., Philips Research Laboratories Technology of the Diode Programmable Read Only Memory de Vreede L.C.N., Delft University of Technology MAIDS: A Microwave Active Integral Device Simulator Dean M.J., Simon Fraser University, Burnaby, Canada An alternative method to monitor and control the IC temperature in the 4.2-77 K range Decker S., University of Bremen Examination of theTransient Drift-Diffusion and Hydrodynamic Modeling Accuracy for SiGe HBTs by 2D Monte-Carlo Device Simulation Decoutere S., IMEC, Leuven, Belgium Optical testing of submicron-technology MOSFETs and bipolar transistors Deferm L., IMEC --> Closed-form model of the subhalfmicrometer LDD MOSFET overlap capacitance A High Performance 0.18 µm CMOS Technology Designed for Manufacturability Deleonibus S., LETI/CEA, Grenoble A comparative study of three designs of 0.10 µm NMOSFETs processed with heavy ion implanted pocket --> The Oxidized Amorphous Silicon Improved LOCal Isolation (OASI-LOCI) concept Delorme N., LETI/CEA, Grenoble Influence of substrate type on interconnect peformance DeMeyer K., IMEC, Leuven, Belgium --> An Improved Technology for Elevated Source/Drain MOSFETS DeSantis J., National Semiconductor Cor. Effects of processing temperatures on device design rules for Silicon/Silicon Germanium heterojunction bipolar transistors Devine R.A.B., France Telecom - CNET Comparative hot carrier induced degradation in 0,25 µm MOSFETs with H or D passivated interfaces Diawuo K., University of Newcastle Performance limits of deep submicron buried channel delta doped MOSFETs Dietrich H., Temic Telefunken Microelectronic, Heilbronn, Germany Low-Noise Amplifier for Mobile Communications using a Production Ready SiGe HBT Technology Digele G., Robert Bosch GmbH Electro-Thermal Interaction on Circuit Level under the Influence of Packaging Dimitriadis C., NCSR "DEMOCRITOS" A Stress Technique Suitable For The In-Line Reliability Monitoring Of The Hot Carrier Endurance of Sub-0,5um MOSFETs Diskus C.G., University of Linz Transferred Electron Effect in AlGaAs/GaAs Multi-Quantum-Well Structures Dollfus P., Université Paris XI Predictive expression of propagation delay in short channel CMOS/SOI inverter using Monte Carlo simulation Dori L., CNR LAMEL - Institute A novel gas sensor for hydrocarbons detection based on porous silicon permeated with Sn-V mixed oxides Dubois E., Inst. Supérieur d'Electronique Nord Impact of non-equilibrium transport and series resistances in 0.1µm bulk and SOI MOSFETs Dubois E., IEMN/ISEN Nanometer Scale Lithography of Silicon and Titanium using Scanning Probe Microscopy Dubuc J.P., ENSPM New parameter extraction method for the simulation of the space charge created by Fowler-Nordheim electron injections in the gate oxide of MOS devices Dudek V., Institute for Microelectronics, Stuttgart, Germany Studies on the heat removal features of stacked SOI structures with a dedicated field solver program (SUNRED) E Realization and Evaluation of an Ultra Low-Voltage/Low-Power 0.25µm (n+/p+) Dual-Workfunction CMOS Technology Eisele I., Universität der Bundeswehr München The Planar-Doped-Barrier-FET: MOSFET Overcomes Conventional Limitations Emons C.H.H., Philips Research Laboratories A 34 GHz fT Bipolar Process with High-Energy-Implanted Collector Erben U., University of Ulm Low-Noise Amplifier for Mobile Communications using a Production Ready SiGe HBT Technology Evans A.G.R., University of Southampton --> An Improved Technology for Elevated Source/Drain MOSFETS F A cost effective smart power technology for 45V applications Fawaz H., IEMN-DHS A fully GaAs-based 100MHz, 2W DC-to-DC Power Converter Faynot O., LETI/CEA, Grenoble, France Temperature dependence (300-600K) of parasitic bipolar effects in SOI-MOSFETs Fehly D., Technische Universität Braunschweig Vibration sensor with optoelectronic interface Fiorini M., CNR LAMEL - Institute A novel gas sensor for hydrocarbons detection based on porous silicon permeated with Sn-V mixed oxides Fischer G., Institute for Semiconductor Physics CMOS Production Compatible SiGe Heteroepitaxy for High Frequency Circuits Control of steep Boron profiles in Si/SiGe heterojunction bipolar transistors Flack R., National Semiconductor Cor. A Reflective-mode PDLC Light Valve Display Technology Foley S., Nat. Microelectronics Research Centre Finite Element Analysis of Stress Distributions in Interconnect Structures Folkmer B., HSG-IMIT --> New Designs, Readout Concept and Simulation Approach of Micromachined Rate Gyroscopes Fontaine P.A., IEMN/ISEN Nanometer Scale Lithography of Silicon and Titanium using Scanning Probe Microscopy Fortunato G., IESS-CNR Noise performances and hot carrier efects in polysilicon thin film transistors Frazee J., National Semiconductor Cor. A Reflective-mode PDLC Light Valve Display Technology Fricke K., Technische Universität Braunschweig Vibration sensor with optoelectronic interface Fukuoka T., Tohoku University --> Polyimide Optical Waveguide with Multi-Fan-Out for Multichip Module Application Fürböck C., TU Vienna A Study of Temperature Distribution in SOI-Smart Power Devices in Transient Conditions by Optical Interferometry Optical testing of submicron-technology MOSFETs and bipolar transistors Furuya H., Toshiba Corporation Limitations of Double Polysilicon Self-Aligned Bipolar Transistor Structure G Low-Frequency Noise Characteristics of Advanced Si and SiGe Bipolar Transistors Galdin S., Université Paris XI Predictive expression of propagation delay in short channel CMOS/SOI inverter using Monte Carlo simulation Gamble H.S., Northern Ireland Semicon. Res. Cen. Enhancement of TFT Performance by Low Temperature Oxygen Annealing Gámiz F., Universidad de Granada Monte Carlo study on electron transport properties in double-gate fully depleted SOI-MOSFETs Garbar N., Institute of Semiconductor Physics, Kiev, Ukraine --> RTS diagnostics of source-drain (edge?) related defects in submicron n-MOSFETs Garulli A., CNR LAMEL - Institute A novel gas sensor for hydrocarbons detection based on porous silicon permeated with Sn-V mixed oxides Gatti E., Politecnico di Milano A new numerical method for determining the excess noise power spectrum in MOSFETs Geiger W., HSG-IMIT --> New Designs, Readout Concept and Simulation Approach of Micromachined Rate Gyroscopes Geraci A., Politecnico di Milano A new numerical method for determining the excess noise power spectrum in MOSFETs Ghibaudo G., LPCS/ENSERG, Grenoble, France Stress induced leakage current dependence on oxide thickness, technology and stress level Ghibaudo G., ENSERG, Grenoble, France New parameter extraction method for the simulation of the space charge created by Fowler-Nordheim electron injections in the gate oxide of MOS devices Ghibaudo G., LCPS, ENSERG/INPG, Grenoble, France Low frequency 1/f noise characterization of advanced CMOS-compatible bipolar junction transistors for technology evaluation Ghibaudo G., LPCS, ENSERG, Grenoble Hot Carrier effects and time-dependent degradation laws in 0.1µm bulk Si n-MOSFETs Ghidini G., SGS-Thomson Microelectronics, Agrate Brianza,Italy Stress induced leakage current dependence on oxide thickness, technology and stress level Ghioni M., Politecnico di Milano Integrated array of avalanche photodiodes for single-photon counting Gießmann J., Meissner & Wurst GmbH+Co Stategic Alliances for highly efficient 300 mm Waferfabs Giovannini S., IESS-CNR Noise performances and hot carrier efects in polysilicon thin film transistors Gladkikh A., Tel Aviv University Correlation between electromigration damage kinetics and microstructure in Cu interconnects Goguenheim D., ISEM Toulon Effects of high temperature on performances and hot-carrier reliability in DC/AC stressed 0.35 µm n-MOSFETs Gornik E., TU Vienna A Study of Temperature Distribution in SOI-Smart Power Devices in Transient Conditions by Optical Interferometry Optical testing of submicron-technology MOSFETs and bipolar transistors Goser K., University of Dortmund, Germany Periodic Transconductance Oscillations in Sub-100nm MOSFETs Goser K., University of Dortmund Detailed Matching Analysis of Sub-50 nm-MOS-Transistors Goto H., Fujitsu Limited, Kawasaki, Japan Investigation of the influence of impact ionization feedback on the spatial distribution of hot carriers in an NMOSFET Goto K., Tohoku University Fabrication of 0.1 µ m MOSFET with Super Self-Aligned Ultrashallow Junction Electrodes Using Selective Si1-x Gex CVD Graf P., University of Bremen Examination of theTransient Drift-Diffusion and Hydrodynamic Modeling Accuracy for SiGe HBTs by 2D Monte-Carlo Device Simulation Graf H.G., Inst. f. Mikroelektronik Stuttgart, Germany Flexible Micro-Photodiode Array as a Subretinal Implant Graf M., Inst. f. Mikroelektronik Stuttgart, Germany Flexible Micro-Photodiode Array as a Subretinal Implant Graffi S., University of Bologna A Unified Approach for Modeling Multiterminal Bipolar and MOS Devices in Smart-Power Technologies Grapputo N., Università di Padova HBM and CDM ESD stress test results in 0.6 µm CMOS structures Grasser T., TU Vienna A Physically Based Substrate Current Simulation Guegan G., LETI/CEA, Grenoble Building in reliability with latch-up, ESD and hot carrier effects on a 0.25 µm CMOS technology A comparative study of three designs of 0.10 µm NMOSFETs processed with heavy ion implanted pocket Guibert J.-C., LETI/CEA, Grenoble --> The Oxidized Amorphous Silicon Improved LOCal Isolation (OASI-LOCI) concept Guillaumot B., SGS-Thomson Microelectronics Thinning Oxide-Nitride-Oxide Interpoly Dielectric (11-13nm) for 0.25 µm Flash Cell Memories Guillaumot B., SGS-Thomson Microelectronics, Crolles, France Theoretical Analysis of a Pseudo-Floating Gate flash EEPROM Device Gutiérrez-D. E. A,, INAOE An alternative method to monitor and control the IC temperature in the 4.2-77 K range Gwoziecki R., France Telecom - CNET Junctions design guidelines for 0.18µm CMOS SiGe gate for highly performant 0.15/0.18µm CMOS technology H A Study of Temperature Distribution in SOI-Smart Power Devices in Transient Conditions by Optical Interferometry Optical testing of submicron-technology MOSFETs and bipolar transistors Haga D., Royal Institute of Technology An InP-HBT technology for monolithic optoelectronic receivers with 24 GHz bandwidth Halimaoui A., France Telecom - CNET SiGe gate for highly performant 0.15/0.18µm CMOS technology Hall S., University of Liverpool, United Kingdom The Design and Characterisation of a SiGe I²L Technology Hall S., The University of Liverpool --> Realisation of a 0.1 µm vertical MOSFET with a SiGe source Hamaguchi C., Osaka University, Japan Dynamic floating body effects in PD SOI MOSFETs biased in the kink region Hammerl E., Siemens AG As and B Diffusion in TiSi2/Polysilicon Gates with Dual Workfunction Gate Technology Han T.-H., Electronics and Telecom. Res. Inst. A 9 GHz Bandwith Preamplifier in 10 Gbps Optical Receiver Using SiGe Base HBT Haneder T., University of Regensburg Optimisation of Ultra High Density MOS Arrays in 3D Hansch W., Universität der Bundeswehr München The Planar-Doped-Barrier-FET: MOSFET Overcomes Conventional Limitations Haond M., SGS-Thomson Microelectronics 0.25 µm NMOS transistor with nitride spacer: reduction of the short channel effect by optimisation of the gate reoxidation process and reliablity Haond M., France Telecom - CNET, Meylan, France --> Enhanced hot-carrier induced degradation in STI isolated NMOS transistors Harmand J.-C., France Telecom - CNET-DTD, Bagneux, France High Frequency Analysis of InP Transistors versus Temperature Harrison B., Griffith University, Brisbane, Australia Electrical modelling of Kelvin structures for the derivation of low specific contact resistivity Hart C.M., Philips Research Laboratories Technology of the Diode Programmable Read Only Memory Hechtl Ch., Texas Instruments Gmbh Germany --> Enhanced Breakdown Voltage and Charge to Breakdown of Collector Implant-Gate Oxide-Poly Capacitors by Selective Epitaxial Growth Heinemann B., Institute for Semiconductor Physics Control of steep Boron profiles in Si/SiGe heterojunction bipolar transistors Heinrich R., Siemens AG Low-Cost CMOS Process with Complete Post-Gate Implantation Scheme Heitzmann M., LETI/CEA, Grenoble A comparative study of three designs of 0.10 µm NMOSFETs processed with heavy ion implanted pocket --> The Oxidized Amorphous Silicon Improved LOCal Isolation (OASI-LOCI) concept Hendriks M., Philips Semiconductors, Nijmegen, Netherlands A High Performance 0.18 µm CMOS Technology Designed for Manufacturability Hernandez C., France Telecom - CNET An investigation of polysilicon emitter bipolar transistors with an ozonized polysilicon/monosilicon interface Hesto P., Université Paris XI Predictive expression of propagation delay in short channel CMOS/SOI inverter using Monte Carlo simulation Hierzenberger A., University of Stuttgart Flexible Micro-Photodiode Array as a Subretinal Implant Hilleringmann U., University of Dortmund, Germany Periodic Transconductance Oscillations in Sub-100nm MOSFETs Hilleringmann U., University of Dortmund Detailed Matching Analysis of Sub-50 nm-MOS-Transistors Hirano M., NTT Systems Electronics Labs. --> Novel Fabrication Technology for Ultra-Compact Three-Dimensional MMICs Hodges D.A., University of California Benchmarking Semiconductor Manufacturing Höfflinger B., Institute for Microelectronics, Stuttgart, Germany Studies on the heat removal features of stacked SOI structures with a dedicated field solver program (SUNRED) Hofmann F., Siemens AG, Munich, Germany Optimisation of Ultra High Density MOS Arrays in 3D Holland A.S., Royal Melbourne Inst. of Technology Electrical modelling of Kelvin structures for the derivation of low specific contact resistivity Hollensteiner E., TU Vienna --> A Novel Diffusion Coupled Oxidation Model Horan J., Cork Regional Technical College Rapid IC Performance Yield and distribution prediction using a rotation of the circuit parameter principals components Horstmann J., University of Dortmund, Germany Periodic Transconductance Oscillations in Sub-100nm MOSFETs Horstmann J.T., University of Dortmund Detailed Matching Analysis of Sub-50 nm-MOS-Transistors Hossin M., University of Newcastle GaAs Schottky Gate bipolar transistors for high voltage power switching applications Howard D.J., IMEC, Leuven, Belgium --> An Improved Technology for Elevated Source/Drain MOSFETS Hsiao T. C., Advanced Micro Devices Inc., Sunnyvale Source/Drain Engineering with Ge Large Angle Tilt Implantation and Pre-Amorphization to Improve Currrent Drive and Alleviate Floating Body Effects of Thin Film SOI MOSFETs Huber D., Swiss Federal Inst. of Technology 18 GHz high gain monolithically integrated InP/InGaAs PIN/HBT-Receiver Hueting R.J.E., Delft University of Technology Inverse SiGe Heterojunction Bipolar Transistor Huh K., LG Semicon Co., Ltd. New anti-punchthrough design for buried channel PMOSFET Hurkx G.A.M., Philips Research Laboratories Selectively-Implanted Collector Profile Optimisation for High-Speed Vertical Bipolar Transistors Hurt M., University of Virginia, Charlottesville, United States Parasitic bipolar effects leading to on-state breakdown in 2D-MESFETs Hwang J., LG Semicon Co., Ltd. New anti-punchthrough design for buried channel PMOSFET I --> A Manufacturable 0.35 µm BiCMOS using Self-Aligned Cobalt SilicideTechnology Ihn T.-H., Seoul National University --> A new structure for reduction of the leakage currrent in the low temperature Poly-Si TFTs fabricated by the MILC process Ilegems M., Swiss Federal Institute of Technology Two-stage degradation of submicron LDD n-MOSFETs by 1/f noise, charge pumping, and drain current measurements Inoh K., Toshiba Corporation Limitations of Double Polysilicon Self-Aligned Bipolar Transistor Structure Ishibashi S., Toshiba DRAM Technologies For Today`s Market And Future DRAM Generations Ishii M., Tohoku University Fabrication of 0.1 µ m MOSFET with Super Self-Aligned Ultrashallow Junction Electrodes Using Selective Si1-x Gex CVD Itoh Y., NEC Corporation, Kawasaki, Japan --> Measurement of Channel Length and Off-set Region Length for Off-set Gate MOSFETs Iwai H., Toshiba Corp. --> Tunneling gate oxide MOSFET technology J 18 GHz high gain monolithically integrated InP/InGaAs PIN/HBT-Receiver Janssen P.J.M, Philips Research Laboratories Technology of the Diode Programmable Read Only Memory Janssen A.C.L., Philips Semiconductors, Nijmegen A 34 GHz fT Bipolar Process with High-Energy-Implanted Collector Jeon M.-S., Hanyang University, Seoul, Korea --> Patterning of Pt/RuO2 electrodes for Pb(Zr,Ti)O3 in an Inductively Coupled Cl2/O2 Plasma Johnson C. M., University of Newcastle GaAs Schottky Gate bipolar transistors for high voltage power switching applications Joo S.-K., Seoul National University Two-Step Deposition Method for Improvement of the Electrical Characteristics of BST Thin Films --> A new structure for reduction of the leakage currrent in the low temperature Poly-Si TFTs fabricated by the MILC process Joubert O., CNRS LPCM UMR, Nantes, France SiGe gate for highly performant 0.15/0.18µm CMOS technology Jumpertz R., Forschungszentrum Jülich --> Piezoresistive bridge configuration for atomic force microscopy Jung H.S., Inha University --> Patterning of Pt/RuO2 electrodes for Pb(Zr,Ti)O3 in an Inductively Coupled Cl2/O2 Plasma Jungemann C., University of Bremen Investigation of the influence of impact ionization feedback on the spatial distribution of hot carriers in an NMOSFET K Effects of processing temperatures on device design rules for Silicon/Silicon Germanium heterojunction bipolar transistors Kaiblinger-Grujin G., TU Vienna Reexamination of Electron Mobility Dependence on Dopants in GaAs Karpovski M., Tel Aviv University Correlation between electromigration damage kinetics and microstructure in Cu interconnects Kasper E., University of Stuttgart Influence of CMOS-circuit areas on RF-damping of gold and aluminium microstripline in combined SIMMWIC-CMOS technology Kasper E., University of Stuttgart, Germany Electro-Thermal Interaction on Circuit Level under the Influence of Packaging Katsumata Y., Toshiba Corporation Limitations of Double Polysilicon Self-Aligned Bipolar Transistor Structure Katsumata Y., Toshiba Corp. --> Tunneling gate oxide MOSFET technology Keith S., Universität Bremen Full Band Monte-Carlo Device Simulation of an 0.1 µm N-Channel MOSFET in Strained Silicon Material Kelaidis C., NCSR "DEMOKRITOS", Greece Theoretical Analysis of a Pseudo-Floating Gate flash EEPROM Device Keller S., University of Cambridge Development of the Next Generation of Insulated Gate Bipolar Tranistors based on Trench Technology Kennedy G.P., University of Southampton The Design and Characterisation of a SiGe I²L Technology Kerber M., Siemens AG Low-Cost CMOS Process with Complete Post-Gate Implantation Scheme Kerr J.A., GEC Plessey Semiconductors, Lincoln, UK Surface recombination velocity measurement in SPEG SOS MOSFETs by bipolar gain characterisation Khan M.A., APA Optics Inc. GaN based devices for electronic applications Khmyrova I., The University of Aizu Analysis of electron spreadinge effects in pixelless quantum well imaging devices Kibarian J. K., PDF Solutions Statisitcal Analysis for IC-Management Kil D.-S., Seoul National University Two-Step Deposition Method for Improvement of the Electrical Characteristics of BST Thin Films Kim Y.T., Korea Inst. of Science and Technol. C-V characteristics of Pt/SrBi2Ta2O9/CeO2/Si structure for non-volatile memory devices Kirtsch J., France Telecom - CNET A performance comparison between 0.35µm self-aligned and quasi-self-aligned double-polysilicon bipolar transistors Kirtsch J., SGS-Thomson Microelectronics, Crolles An investigation of polysilicon emitter bipolar transistors with an ozonized polysilicon/monosilicon interface Klaassen D.B.M., Philips Research Laboratories, Eindhoven, Netherlands Efficient Parameter Extraction and Statistical Analysis for a 0.25µm low-power CMOS Process Klein P., Siemens AG A Consistent Parameter Extraction Method for Deep Submicron MOSFETs Klose H., Siemens AG DRAM Technologies For Today`s Market And Future DRAM Generations Knaipp M., TU Vienna A Physically Based Substrate Current Simulation Knite M., Riga Technical University Laser induced reversible change of electrical resistivity of CoSi2 thin film Knoll D., Institute for Semiconductor Physics CMOS Production Compatible SiGe Heteroepitaxy for High Frequency Circuits Control of steep Boron profiles in Si/SiGe heterojunction bipolar transistors Kobayashi H., National Defense Academy Slot-antenna-coupled microbolometers for far-infrared detection Kohári Zs., Technical University of Budapest Studies on the heat removal features of stacked SOI structures with a dedicated field solver program (SUNRED) Kol´dyaev V.I., IMEC --> Closed-form model of the subhalfmicrometer LDD MOSFET overlap capacitance König U., Daimler Benz Research --> SiGe/Si-Heterostructure Devices - Status, Problems and Prospects Köpf Ch., TU Vienna Reexamination of Electron Mobility Dependence on Dopants in GaAs Koshevaya S.V., INAOE An alternative method to monitor and control the IC temperature in the 4.2-77 K range Kosina H., TU Vienna Reexamination of Electron Mobility Dependence on Dopants in GaAs Koyanagi M., Tohoku University Two-dimensional analytical model of subthreshold current in fully-depleted SOI MOSFETs --> Polyimide Optical Waveguide with Multi-Fan-Out for Multichip Module Application Fabrication of 0.1 µ m MOSFET with Super Self-Aligned Ultrashallow Junction Electrodes Using Selective Si1-x Gex CVD Kozlowski R., IEMN-DHS A fully GaAs-based 100MHz, 2W DC-to-DC Power Converter Krautschneider W., Siemens AG, Munich, Germany Optimisation of Ultra High Density MOS Arrays in 3D Krick J., Texas Instruments Gmbh Germany --> Enhanced Breakdown Voltage and Charge to Breakdown of Collector Implant-Gate Oxide-Poly Capacitors by Selective Epitaxial Growth Krieg R., Siemens AG Realization and Evaluation of an Ultra Low-Voltage/Low-Power 0.25µm (n+/p+) Dual-Workfunction CMOS Technology Suppression of the Reverse Short Channel Effect in (Sub-)0.25µm nMOSFETs using elevated S/D structures Krüger D., Institute for Semiconductor Physics Control of steep Boron profiles in Si/SiGe heterojunction bipolar transistors Kubicek S., IMEC Investigation of the effect of the extension implant energy on deep submicron CMOS device performance The impact of the S/D extensions on the drain current characteristics of deep submicron Si nMOSFETs at 77 K Kubicek S., IMEC, Leuven, Belgium Optical testing of submicron-technology MOSFETs and bipolar transistors --> An Improved Technology for Elevated Source/Drain MOSFETS Kubo S., Mitsubishi Electric Corporation --> A Manufacturable 0.35 µm BiCMOS using Self-Aligned Cobalt SilicideTechnology Kudoh Y., Tohoku University Fabrication of 0.1 µ m MOSFET with Super Self-Aligned Ultrashallow Junction Electrodes Using Selective Si1-x Gex CVD Kühn C., Universität der Bundeswehr A New Method for Verification of MOSFET Models Based on Device Parameter Variations Kuo D.S., Taiwan Semiconductor Manufacturing A 0.5 µm Flash Technology suitable for Low Voltage Embedded Applications Kuo J.B., National Taiwan University --> Analysis of Capacitance Behavior for Short-Channel Accumulation-Mode SOI PMOS Devices Kurino H., Tohoku University Two-dimensional analytical model of subthreshold current in fully-depleted SOI MOSFETs --> Polyimide Optical Waveguide with Multi-Fan-Out for Multichip Module Application L --> Enhanced hot-carrier induced degradation in STI isolated NMOS transistors Lacaita A., Politecnico di Milano Dynamic floating body effects in PD SOI MOSFETs biased in the kink region Lacaita A.L., Politecnico di Milano Determination of interface state density of ULSI n-MOSFET by 1/f noise measurements Ladner C., France Telecom - CNET-DTD, Bagneux, France High Frequency Analysis of InP Transistors versus Temperature Lammers A.M.F., Philips Research Laboratories Al-n-Si Double-Schottky Photodiodes for Optical Storage Systems Lang W., HSG-IMIT --> New Designs, Readout Concept and Simulation Approach of Micromachined Rate Gyroscopes Laurens M., SGS-Thomson Microelectronics, Crolles, France Low frequency 1/f noise characterization of advanced CMOS-compatible bipolar junction transistors for technology evaluation Leachman R.C., University of California Benchmarking Semiconductor Manufacturing Lecontellec M., SGS-Thomson Microelectronics 0.25 µm NMOS transistor with nitride spacer: reduction of the short channel effect by optimisation of the gate reoxidation process and reliablity Leduc J.-V., Philips Research Laboratories Al-n-Si Double-Schottky Photodiodes for Optical Storage Systems Lee J.G., Inha University --> Patterning of Pt/RuO2 electrodes for Pb(Zr,Ti)O3 in an Inductively Coupled Cl2/O2 Plasma Lee J.D., Seoul National University Lateral Channel Doping Engineering in 0.1µm Recessed Channel nMOSFETs Lee S.-M., Electronics and Telecom. Res. Inst. A 9 GHz Bandwith Preamplifier in 10 Gbps Optical Receiver Using SiGe Base HBT Lee S., LG Semicon Co., Ltd. New anti-punchthrough design for buried channel PMOSFET Lee Y., LG Semicon Co., Ltd. New anti-punchthrough design for buried channel PMOSFET Lee B.-I., Seoul National University Two-Step Deposition Method for Improvement of the Electrical Characteristics of BST Thin Films --> A new structure for reduction of the leakage currrent in the low temperature Poly-Si TFTs fabricated by the MILC process Lee H.N., Korea Inst. of Science and Technol. C-V characteristics of Pt/SrBi2Ta2O9/CeO2/Si structure for non-volatile memory devices Lee B., Northern Ireland Semicon. Res. Cen. Enhancement of TFT Performance by Low Temperature Oxygen Annealing Leech P.W., CSIRO, Clayton, Australia Electrical modelling of Kelvin structures for the derivation of low specific contact resistivity Leipold D., Texas Instruments Gmbh Germany --> Enhanced Breakdown Voltage and Charge to Breakdown of Collector Implant-Gate Oxide-Poly Capacitors by Selective Epitaxial Growth Leitner E., TU Vienna --> A Novel Diffusion Coupled Oxidation Model Leone A., University of Bologna A Unified Approach for Modeling Multiterminal Bipolar and MOS Devices in Smart-Power Technologies Lerme M., LETI CEA Grenoble Multi Layer Metallization Leroux C., LETI/CEA, Grenoble Building in reliability with latch-up, ESD and hot carrier effects on a 0.25 µm CMOS technology Liang M.S., Taiwan Semiconductor Manufacturing A 0.5 µm Flash Technology suitable for Low Voltage Embedded Applications Lifka H., Philips Research Laboratories Technology of the Diode Programmable Read Only Memory Lin P.-H., National Cheng-Kung University A Novel Functional Heterostructure-Emitter and Hereostructure-Base Transistor (HEHBT) Lin Y.F., Taiwan Semiconductor Manufacturing A 0.5 µm Flash Technology suitable for Low Voltage Embedded Applications Lindenkreuz S., Robert Bosch GmbH Electro-Thermal Interaction on Circuit Level under the Influence of Packaging Lippert G., Institute for Semiconductor Physics Control of steep Boron profiles in Si/SiGe heterojunction bipolar transistors List F.J., Philips Semiconductors, Eindhoven, Netherlands A 0.5 µm Flash Technology suitable for Low Voltage Embedded Applications Liu W.-C., National Cheng-Kung University A Novel Functional Heterostructure-Emitter and Hereostructure-Base Transistor (HEHBT) Liu H.C., National Research Council, Ottawa, Canada Analysis of electron spreadinge effects in pixelless quantum well imaging devices Liu P., University of California Source/Drain Engineering with Ge Large Angle Tilt Implantation and Pre-Amorphization to Improve Currrent Drive and Alleviate Floating Body Effects of Thin Film SOI MOSFETs Llinares P., France Telecom - CNET Low frequency 1/f noise characterization of advanced CMOS-compatible bipolar junction transistors for technology evaluation Longoni A., Politecnico di Milano Determination of interface state density of ULSI n-MOSFET by 1/f noise measurements A new numerical method for determining the excess noise power spectrum in MOSFETs López-Villanueva J.A., Universidad de Granada Monte Carlo study on electron transport properties in double-gate fully depleted SOI-MOSFETs Lorenz J., Fraunhofer-Institut, Erlangen, Germany Three-Dimensional Simulation of Contact Hole Metallization using Aluminum Sputter Deposition at Elevated Temperatures Lormand G., GEMPPM - INSA - UMRCNRS, Villeurbanne Thermal analytical model for analysis of pulsed DC electromigration results Lormang G., GEMPPM - INSA - UMRCNRS, Villeurbanne, France Influence of thermal heating effect on pulsed DC electromigration result analysis Lübke K., University of Linz Transferred Electron Effect in AlGaAs/GaAs Multi-Quantum-Well Structures Lukyanchikova N., Institute of Semiconductor Physics, Kiev, Ukraine --> RTS diagnostics of source-drain (edge?) related defects in submicron n-MOSFETs Luttrell R., National Semiconductor Cor. A Reflective-mode PDLC Light Valve Display Technology Luy J.-F., Daimler Benz AG A 73 GHz SiGe SIMMWIC module Lyden C., National Microelectronics Research Centre Rapid IC Performance Yield and distribution prediction using a rotation of the circuit parameter principals components Lynch W.T., Semiconductor Research Corp. Triangel Research Park, USA Source/Drain Engineering with Ge Large Angle Tilt Implantation and Pre-Amorphization to Improve Currrent Drive and Alleviate Floating Body Effects of Thin Film SOI MOSFETs Lyu J., Seoul National University Lateral Channel Doping Engineering in 0.1µm Recessed Channel nMOSFETs M Dynamic floating body effects in PD SOI MOSFETs biased in the kink region Maezawa K., NTT Systems Electronics Labs., Kanagawa, Japan High-Frequency Small-Signal and Large-Signal Characteristics of Resonant Tunneling High Electron Mobility Transistors Marchand B., LPCS, ENSERG, Grenoble Hot Carrier effects and time-dependent degradation laws in 0.1µm bulk Si n-MOSFETs Marek J., Robert Bosch GmbH Silicon Microsystems for Automotive Applications Mariucci L., IESS-CNR Noise performances and hot carrier efects in polysilicon thin film transistors Martin M.J., Universidad de Salamanca Monte Carlo comparative study of current-mode noise in Si/Si 1-x Ge x Strained Heterojunctions Martin F., LETI/CEA, Grenoble A comparative study of three designs of 0.10 µm NMOSFETs processed with heavy ion implanted pocket --> The Oxidized Amorphous Silicon Improved LOCal Isolation (OASI-LOCI) concept Thinning Oxide-Nitride-Oxide Interpoly Dielectric (11-13nm) for 0.25 µm Flash Cell Memories Martinotti P., SGS Thomson Microelectronics Human Capital for Growth in Microelectronics (The Brain Intensive Era) Marty-Blavier A., Motorola A cost effective smart power technology for 45V applications Martynov J.B., State Research Institute "Pulsar" Simulation of avalanche injection filamentation in MOSFET's and IGBT's Martynov Y.B., State Research Institute "Pulsar" Microplasma and Uniform Gate Breakdown in MESFETs Masetti C., University of Bologna A Unified Approach for Modeling Multiterminal Bipolar and MOS Devices in Smart-Power Technologies Mathewson A., National Microelectronics Research Centre Efficient Parameter Extraction and Statistical Analysis for a 0.25µm low-power CMOS Process Mathewson A., NMRC, Cork, Ireland A Stress Technique Suitable For The In-Line Reliability Monitoring Of The Hot Carrier Endurance of Sub-0,5um MOSFETs Mathewson A., Nat. Microelectronics Research Centre Finite Element Analysis of Stress Distributions in Interconnect Structures Mathewson A., National Microelectronic Research Centre, Cork, Ireland Integrated array of avalanche photodiodes for single-photon counting Mathewson A., Nat. Microelectron. Res. Cent. Cork Theoretical Analysis of a Pseudo-Floating Gate flash EEPROM Device Matsumoto T., Tohoku University --> Polyimide Optical Waveguide with Multi-Fan-Out for Multichip Module Application Matsuura T., Tohoku University Fabrication of 0.1 µ m MOSFET with Super Self-Aligned Ultrashallow Junction Electrodes Using Selective Si1-x Gex CVD McCarthy K.G., National Microelectronics Research Centre Efficient Parameter Extraction and Statistical Analysis for a 0.25µm low-power CMOS Process Medvid´ A., Riga Technical University Laser induced reversible change of electrical resistivity of CoSi2 thin film Meinerzhagen B., University of Bremen Examination of theTransient Drift-Diffusion and Hydrodynamic Modeling Accuracy for SiGe HBTs by 2D Monte-Carlo Device Simulation Meinerzhagen B., Universität Bremen Full Band Monte-Carlo Device Simulation of an 0.1 µm N-Channel MOSFET in Strained Silicon Material Meister T.F., Siemens AG Low-Frequency Noise Characteristics of Advanced Si and SiGe Bipolar Transistors Meneghesso G., Università di Padova HBM and CDM ESD stress test results in 0.6 µm CMOS structures Parasitic bipolar effects leading to on-state breakdown in 2D-MESFETs Millington A., GEC Plessey Semiconductors, Lincoln, UK Development of the Next Generation of Insulated Gate Bipolar Tranistors based on Trench Technology Mitchell S.J.N., Northern Ireland Semicon. Res. Cen. Enhancement of TFT Performance by Low Temperature Oxygen Annealing Mo S., Technische Universität Braunschweig Vibration sensor with optoelectronic interface Mohammed-Brahim T., Site Universitaire Gate bias aging of unhydrogenated polycrystalline silicon TFTs Moiseiwitsch N.E., University of Southampton The Design and Characterisation of a SiGe I²L Technology Momose H.S., Toshiba Corp. --> Tunneling gate oxide MOSFET technology Mondon F., Université Joseph Fourier, Grenoble, France Thinning Oxide-Nitride-Oxide Interpoly Dielectric (11-13nm) for 0.25 µm Flash Cell Memories Monroy A., SGS-Thomson Microelectronics, Crolles An investigation of polysilicon emitter bipolar transistors with an ozonized polysilicon/monosilicon interface Montree A.H., Philips Research Laboratories Study of pocket implant parameters for 0,18 µm CMOS Moore P., National Semiconductor Cor. A Reflective-mode PDLC Light Valve Display Technology Morf T., Swiss Federal Inst. of Technology 18 GHz high gain monolithically integrated InP/InGaAs PIN/HBT-Receiver Morrison A., National Microelectronic Research Centre, Cork, Ireland Integrated array of avalanche photodiodes for single-photon counting Mortini P., SGS-Thomson Microelectronics, Crolles, France Effects of high temperature on performances and hot-carrier reliability in DC/AC stressed 0.35 µm n-MOSFETs Mourgues K., Université de Rennes I, France Gate bias aging of unhydrogenated polycrystalline silicon TFTs Mourrain C., France Telecom - CNET SiGe gate for highly performant 0.15/0.18µm CMOS technology Mouthaan K., Delft University of Technology Thermal resistance modelling of RF high power bipolar transistors Murota J., Tohoku University Fabrication of 0.1 µ m MOSFET with Super Self-Aligned Ultrashallow Junction Electrodes Using Selective Si1-x Gex CVD Myers E.R., National Semiconductor Cor. Effects of processing temperatures on device design rules for Silicon/Silicon Germanium heterojunction bipolar transistors N Limitations of Double Polysilicon Self-Aligned Bipolar Transistor Structure Nakamura S.-I., Toshiba Corp. --> Tunneling gate oxide MOSFET technology Nakashima T., Mitsubishi Electric Corporation --> A Manufacturable 0.35 µm BiCMOS using Self-Aligned Cobalt SilicideTechnology Nanver L.K., Delft University of Technology Self-aligned metallization of high-frequency BJT´s with low-stress silicon-nitride spacers Inverse SiGe Heterojunction Bipolar Transistor Narr A., Siemens Semiconductor Division, Munich, Germany Realization and Evaluation of an Ultra Low-Voltage/Low-Power 0.25µm (n+/p+) Dual-Workfunction CMOS Technology Naruse H., Toshiba Corporation Limitations of Double Polysilicon Self-Aligned Bipolar Transistor Structure Neidlinger Th., University of Stuttgart Voltage controlled colour separation in two-terminal a-Si:H based sensor structures Neinhüs B., University of Bremen Examination of theTransient Drift-Diffusion and Hydrodynamic Modeling Accuracy for SiGe HBTs by 2D Monte-Carlo Device Simulation Neumueller W., Siemens AG DRAM Technologies For Today`s Market And Future DRAM Generations Neuvo Y., Nokia Mobile Pones RF Moblile Communication Circuits - Comparison of Technologies Neviani A., Università di Padova Parasitic bipolar effects leading to on-state breakdown in 2D-MESFETs Niel S., France Telecom - CNET Low frequency 1/f noise characterization of advanced CMOS-compatible bipolar junction transistors for technology evaluation An investigation of polysilicon emitter bipolar transistors with an ozonized polysilicon/monosilicon interface Nieuwesteeg K.K., Philips Flat Panel Display --> AM-LCDs bring solid-state devices to the display Nii H., Toshiba Corporation Limitations of Double Polysilicon Self-Aligned Bipolar Transistor Structure Nisch W., University of Tübingen, Germany Flexible Micro-Photodiode Array as a Subretinal Implant O GaAs Schottky Gate bipolar transistors for high voltage power switching applications O`Neil A.G., University of Newcastle Performance limits of deep submicron buried channel delta doped MOSFETs Ohlsson O., Nanosensors GmbH, Wetzlar, Germany --> Piezoresistive bridge configuration for atomic force microscopy Ohtsu Y., Ryoden Semiconductor System Eng. Corp., Hyogo, Japan --> A Manufacturable 0.35 µm BiCMOS using Self-Aligned Cobalt SilicideTechnology Okhonin S., Swiss Federal Institute of Technology Two-stage degradation of submicron LDD n-MOSFETs by 1/f noise, charge pumping, and drain current measurements Onodera K., NTT Systems Electronics Labs. --> Novel Fabrication Technology for Ultra-Compact Three-Dimensional MMICs Osten J., Institute for Semiconductor Physics Control of steep Boron profiles in Si/SiGe heterojunction bipolar transistors Oualid J., ENSPM New parameter extraction method for the simulation of the space charge created by Fowler-Nordheim electron injections in the gate oxide of MOS devices P Theory and modelling of organic field effect transistors Paccagnella A., Università di Padova Stress induced leakage current dependence on oxide thickness, technology and stress level Pacelli A., Politecnico di Milano Determination of interface state density of ULSI n-MOSFET by 1/f noise measurements Pages I., Motorola A cost effective smart power technology for 45V applications Palevski A., Tel Aviv University Correlation between electromigration damage kinetics and microstructure in Cu interconnects Pananakakis G., LPCS/ENSERG, Grenoble, France Stress induced leakage current dependence on oxide thickness, technology and stress level Pantel R., France Telecom - CNET An investigation of polysilicon emitter bipolar transistors with an ozonized polysilicon/monosilicon interface Paoli M., France Telecom - CNET SiGe gate for highly performant 0.15/0.18µm CMOS technology Papadas C., SGS-Thomson Microelectronics, Crolles, France Stress induced leakage current dependence on oxide thickness, technology and stress level A Stress Technique Suitable For The In-Line Reliability Monitoring Of The Hot Carrier Endurance of Sub-0,5um MOSFETs Theoretical Analysis of a Pseudo-Floating Gate flash EEPROM Device Pardo D., Universidad de Salamanca Monte Carlo comparative study of current-mode noise in Si/Si 1-x Ge x Strained Heterojunctions Parisini A., CNR LAMEL - Institute A novel gas sensor for hydrocarbons detection based on porous silicon permeated with Sn-V mixed oxides Park S.-G., Inha University --> Patterning of Pt/RuO2 electrodes for Pb(Zr,Ti)O3 in an Inductively Coupled Cl2/O2 Plasma Park B.-G., Seoul National University Lateral Channel Doping Engineering in 0.1µm Recessed Channel nMOSFETs Patel C.J., Middlesex University Surface recombination velocity measurement in SPEG SOS MOSFETs by bipolar gain characterisation Paulzen G.M., Philips Research Laboratories Technology of the Diode Programmable Read Only Memory Pavan P., Università di Modena, Italy HBM and CDM ESD stress test results in 0.6 µm CMOS structures Pavesi M., Università di Parma, Italy Parasitic bipolar effects leading to on-state breakdown in 2D-MESFETs Peatman W.C.B., University of Virginia, Charlottesville, United Staates Parasitic bipolar effects leading to on-state breakdown in 2D-MESFETs Pecora A., IESS-CNR Noise performances and hot carrier efects in polysilicon thin film transistors Peiner E., Technische Universität Braunschweig Vibration sensor with optoelectronic interface Pelloie J.L., LETI/CEA, Grenoblem, France On the determination of the time-dependent degradation laws in deep submicron SOI MOSFETs Perelló C., IMEC A High Performance 0.18 µm CMOS Technology Designed for Manufacturability Perron L., Politecnico di Milano Dynamic floating body effects in PD SOI MOSFETs biased in the kink region Peter M.S., Philips Research Laboratories Selectively-Implanted Collector Profile Optimisation for High-Speed Vertical Bipolar Transistors Petrichuk M.V., Institute of Semiconductor Physics, Kiev, Ukraine --> RTS diagnostics of source-drain (edge?) related defects in submicron n-MOSFETs Pidin S., Tohoku University Two-dimensional analytical model of subthreshold current in fully-depleted SOI MOSFETs Pinto M.R., Lucent Technologies The transistor´s discovery and what´s ahead Pogany D., TU Vienna A Study of Temperature Distribution in SOI-Smart Power Devices in Transient Conditions by Optical Interferometry Optical testing of submicron-technology MOSFETs and bipolar transistors Poggi A., CNR LAMEL - Institute A novel gas sensor for hydrocarbons detection based on porous silicon permeated with Sn-V mixed oxides Politiek J., Philips Research Laboratories A 34 GHz fT Bipolar Process with High-Energy-Implanted Collector Poncet A., France Telecom - CNET Cost effective simulation of three-dimensional effects in the shallow trench isolation process Junctions design guidelines for 0.18µm CMOS Ponomarev Y.V., Philips Research Laboratories Study of pocket implant parameters for 0,18 µm CMOS A 34 GHz fT Bipolar Process with High-Energy-Implanted Collector Proetel D., Texas Instruments Gmbh Germany --> Enhanced Breakdown Voltage and Charge to Breakdown of Collector Implant-Gate Oxide-Poly Capacitors by Selective Epitaxial Growth Puchert T., Texas Instruments Gmbh Germany --> Enhanced Breakdown Voltage and Charge to Breakdown of Collector Implant-Gate Oxide-Poly Capacitors by Selective Epitaxial Growth Q Enhancement of TFT Performance by Low Temperature Oxygen Annealing R --> A Novel Diffusion Coupled Oxidation Model Ramgopal Rao V., University of California, Los Angeles, USA The Planar-Doped-Barrier-FET: MOSFET Overcomes Conventional Limitations Ramgopal Rao V., University of California --> Mechanisms of Localized Charge Injection: A Technique to Characterize Gate Edge Damage in MOS Transistors Raoult F., Site Universitaire Gate bias aging of unhydrogenated polycrystalline silicon TFTs Rauly E., LPCS, ENSERG, Grenoble Hot carrier effect in sub-0.1µm SOI-MOSFETs Raynaud C., LETI/CEA, Grenoble, France Temperature dependence (300-600K) of parasitic bipolar effects in SOI-MOSFETs Reeves G.K., Royal Melbourne Inst. of Technology Electrical modelling of Kelvin structures for the derivation of low specific contact resistivity Regolini J.-L., France Telecom - CNET SiGe gate for highly performant 0.15/0.18µm CMOS technology Reichert G., ENSERG Grenoble Temperature dependence (300-600K) of parasitic bipolar effects in SOI-MOSFETs Reimbold G., LETI/CEA, Grenoble Building in reliability with latch-up, ESD and hot carrier effects on a 0.25 µm CMOS technology Thinning Oxide-Nitride-Oxide Interpoly Dielectric (11-13nm) for 0.25 µm Flash Cell Memories Ren L., Swiss Federal Institute of Technology Two-stage degradation of submicron LDD n-MOSFETs by 1/f noise, charge pumping, and drain current measurements Rencz M., Technical University of Budapest Studies on the heat removal features of stacked SOI structures with a dedicated field solver program (SUNRED) Renn S.H., LPCS, ENSERG, Grenoble On the determination of the time-dependent degradation laws in deep submicron SOI MOSFETs Revil N., SGS-Thomson Microelectronics 0.25 µm NMOS transistor with nitride spacer: reduction of the short channel effect by optimisation of the gate reoxidation process and reliablity Revil N., SGS-Thomson Microelectronics, Crolles, France Effects of high temperature on performances and hot-carrier reliability in DC/AC stressed 0.35 µm n-MOSFETs Rezazadeh A., King's College London --> Analytical modeling of InP/InGaAs HBTs Ries P., LPCS/ENSERG, Grenoble, France Stress induced leakage current dependence on oxide thickness, technology and stress level Risch L., Siemens AG Advanced self aligned SOI concepts for vertical MOS transistors with ultrashort channel lengths --> Recent Progress with Vertical Transistors Ritter G., Institute for Semiconductor Physics CMOS Production Compatible SiGe Heteroepitaxy for High Frequency Circuits Roldán J.B., Universidad de Granada Monte Carlo study on electron transport properties in double-gate fully depleted SOI-MOSFETs Röpke W., Institute for Semiconductor Physics Control of steep Boron profiles in Si/SiGe heterojunction bipolar transistors Roselli L., Università di Perugia Circuit simulation through coordinated EM and solid-state device numerical analyses Rösner W., Siemens AG Advanced self aligned SOI concepts for vertical MOS transistors with ultrashort channel lengths --> Recent Progress with Vertical Transistors Roussin J.C., LETI/CEA, Grenoble A comparative study of three designs of 0.10 µm NMOSFETs processed with heavy ion implanted pocket Roy S., University of Glasgow RF performance of strained Si MODFETs and MOSFETs on "virtual" SiGe substrates: A Monte Carlo study Rücker H., Institute for Semiconductor Physics Control of steep Boron profiles in Si/SiGe heterojunction bipolar transistors Ryssel H., Universität Erlangen-Nürnberg Three-Dimensional Simulation of Contact Hole Metallization using Aluminum Sputter Deposition at Elevated Temperatures Ryum B.R., Electronics and Telecom. Research Institute A 9 GHz Bandwith Preamplifier in 10 Gbps Optical Receiver Using SiGe Base HBT Ryzhii M., The University of Aizu Analysis of electron spreadinge effects in pixelless quantum well imaging devices Ryzhii V., The University of Aizu Analysis of electron spreadinge effects in pixelless quantum well imaging devices S Efficient Parameter Extraction and Statistical Analysis for a 0.25µm low-power CMOS Process Sagnes B., ENSPM New parameter extraction method for the simulation of the space charge created by Fowler-Nordheim electron injections in the gate oxide of MOS devices Sagnes I., France Telecom - CNET SiGe gate for highly performant 0.15/0.18µm CMOS technology An investigation of polysilicon emitter bipolar transistors with an ozonized polysilicon/monosilicon interface Sakuraba M., Tohoku University Fabrication of 0.1 µ m MOSFET with Super Self-Aligned Ultrashallow Junction Electrodes Using Selective Si1-x Gex CVD Sallagoity P., France Telecom - CNET Cost effective simulation of three-dimensional effects in the shallow trench isolation process Sallagoity P., SGS-Thomson Microelectronics --> Enhanced hot-carrier induced degradation in STI isolated NMOS transistors Salmer G., IEMN-DHS A fully GaAs-based 100MHz, 2W DC-to-DC Power Converter Salmer G., IEMN --> Metamorphics: extending the limits of GaAs Salome P., LETI/CEA, Grenoble Building in reliability with latch-up, ESD and hot carrier effects on a 0.25 µm CMOS technology Sandmaier H., HSG-IMIT --> New Designs, Readout Concept and Simulation Approach of Micromachined Rate Gyroscopes Saurenbach F., Surface Imaging Systems GmbH, Herzogenrath, Germany --> Piezoresistive bridge configuration for atomic force microscopy Scarpa A., Università di Padova Stress induced leakage current dependence on oxide thickness, technology and stress level Schäfer H., Siemens AG Suppression of the Reverse Short Channel Effect in (Sub-)0.25µm nMOSFETs using elevated S/D structures Scheinert S., Technische Universität Ilmenau Theory and modelling of organic field effect transistors Schelten J., Forschungszentrum Jülich --> Piezoresistive bridge configuration for atomic force microscopy Schiavone P., France Telecom - CNET SiGe gate for highly performant 0.15/0.18µm CMOS technology Schiekhofer M, Texas Instruments Gmbh Germany --> Enhanced Breakdown Voltage and Charge to Breakdown of Collector Implant-Gate Oxide-Poly Capacitors by Selective Epitaxial Growth Schlachetzki A., Technische Universität Braunschweig --> A new cellular etching-simulator for InP and Si Vibration sensor with optoelectronic interface Schlechtweg et. al. M., Fraunhofer Institute Multifunctional Intergration Using HEMT Technology Schley P., Institute for Semiconductor Physics CMOS Production Compatible SiGe Heteroepitaxy for High Frequency Circuits Control of steep Boron profiles in Si/SiGe heterojunction bipolar transistors Schmitz J., Philips Research Laboratories Study of pocket implant parameters for 0,18 µm CMOS Scholtes T.L.M., Delft University of Technology Inverse SiGe Heterojunction Bipolar Transistor Schubert M.B., University of Stuttgart Flexible Micro-Photodiode Array as a Subretinal Implant Voltage controlled colour separation in two-terminal a-Si:H based sensor structures Schuhmann D., Siemens AG Realization and Evaluation of an Ultra Low-Voltage/Low-Power 0.25µm (n+/p+) Dual-Workfunction CMOS Technology Schulz Th., Siemens AG Advanced self aligned SOI concepts for vertical MOS transistors with ultrashort channel lengths Schumacher H., University of Ulm Low-Noise Amplifier for Mobile Communications using a Production Ready SiGe HBT Technology Schumann D., Siemens AG Suppression of the Reverse Short Channel Effect in (Sub-)0.25µm nMOSFETs using elevated S/D structures Schüppen A., Temic Telefunken Microelectronic, Heilbronn, Germany Low-Noise Amplifier for Mobile Communications using a Production Ready SiGe HBT Technology Schwalke U., Siemens AG Realization and Evaluation of an Ultra Low-Voltage/Low-Power 0.25µm (n+/p+) Dual-Workfunction CMOS Technology Suppression of the Reverse Short Channel Effect in (Sub-)0.25µm nMOSFETs using elevated S/D structures Low-Cost CMOS Process with Complete Post-Gate Implantation Scheme Seibert R., Siemens Semiconductor Division, Munich, Germany Realization and Evaluation of an Ultra Low-Voltage/Low-Power 0.25µm (n+/p+) Dual-Workfunction CMOS Technology Selberherr S., TU Vienna A Physically Based Substrate Current Simulation Reexamination of Electron Mobility Dependence on Dopants in GaAs --> A Novel Diffusion Coupled Oxidation Model Seliger N., TU Vienna A Study of Temperature Distribution in SOI-Smart Power Devices in Transient Conditions by Optical Interferometry Optical testing of submicron-technology MOSFETs and bipolar transistors Seto M, Philips Research Laboratories Al-n-Si Double-Schottky Photodiodes for Optical Storage Systems Shaw C., GEC Plessey Semiconductors, Lincoln, UK Surface recombination velocity measurement in SPEG SOS MOSFETs by bipolar gain characterisation Sheng H., King's College London --> Analytical modeling of InP/InGaAs HBTs Shi L., Philips Semiconductors, Eindhoven, Netherlands A 0.5 µm Flash Technology suitable for Low Voltage Embedded Applications Shieh C.D., Taiwan Semiconductor Manufacturing A 0.5 µm Flash Technology suitable for Low Voltage Embedded Applications Shin D.S., Korea Inst. of Science and Technol. C-V characteristics of Pt/SrBi2Ta2O9/CeO2/Si structure for non-volatile memory devices Shur M., Rensselaer Polytechnic Inst., Troy, United Sates Parasitic bipolar effects leading to on-state breakdown in 2D-MESFETs Shur N.S., Rensselaer Polytechnic Inst. GaN based devices for electronic applications Sicard T., Motorola A cost effective smart power technology for 45V applications Silarays M., Riga Technical University Laser induced reversible change of electrical resistivity of CoSi2 thin film Simoen E., IMEC --> RTS diagnostics of source-drain (edge?) related defects in submicron n-MOSFETs The impact of the S/D extensions on the drain current characteristics of deep submicron Si nMOSFETs at 77 K Sinkevitch V.F., State Research Institute "Pulsar" Simulation of avalanche injection filamentation in MOSFET's and IGBT's Microplasma and Uniform Gate Breakdown in MESFETs Sinnis B., National Microelectronic Research Centre, Cork, Ireland Integrated array of avalanche photodiodes for single-photon counting Skotnicki T., France Telecom - CNET Junctions design guidelines for 0.18µm CMOS SiGe gate for highly performant 0.15/0.18µm CMOS technology Slotboom J., Delft University of Technology MAIDS: A Microwave Active Integral Device Simulator Thermal resistance modelling of RF high power bipolar transistors Slotboom J.W., Philips Research Laboratories, Eindhoven, Netherlands Inverse SiGe Heterojunction Bipolar Transistor Son J., LG Semicon Co., Ltd. New anti-punchthrough design for buried channel PMOSFET Speciale N., University of Bologna A Unified Approach for Modeling Multiterminal Bipolar and MOS Devices in Smart-Power Technologies Springer A.L., University of Linz Transferred Electron Effect in AlGaAs/GaAs Multi-Quantum-Well Structures Sridharan A., University of California --> Mechanisms of Localized Charge Injection: A Technique to Characterize Gate Edge Damage in MOS Transistors Stelzer A., University of Linz Transferred Electron Effect in AlGaAs/GaAs Multi-Quantum-Well Structures Stevens P. B., Middlesex University Surface recombination velocity measurement in SPEG SOS MOSFETs by bipolar gain characterisation Stoisiek M., Siemens AG, Munich, Germany A Study of Temperature Distribution in SOI-Smart Power Devices in Transient Conditions by Optical Interferometry Stopponi G., Università di Perugia Circuit simulation through coordinated EM and solid-state device numerical analyses Strohm K.M., Daimler Benz AG A 73 GHz SiGe SIMMWIC module Su H.D., Taiwan Semiconductor Manufacturing A 0.5 µm Flash Technology suitable for Low Voltage Embedded Applications Su K.W., National Taiwan University --> Analysis of Capacitance Behavior for Short-Channel Accumulation-Mode SOI PMOS Devices Suda K., Mitsubishi Electric Corporation --> A Manufacturable 0.35 µm BiCMOS using Self-Aligned Cobalt SilicideTechnology Sugaya H., Toshiba Corporation Limitations of Double Polysilicon Self-Aligned Bipolar Transistor Structure Sugitani S., NTT Systems Electronics Labs. --> Novel Fabrication Technology for Ultra-Compact Three-Dimensional MMICs Sulzbach Th., Nanosensors GmbH, Wetzlar, Germany --> Piezoresistive bridge configuration for atomic force microscopy Székely V., Technical University of Budapest Studies on the heat removal features of stacked SOI structures with a dedicated field solver program (SUNRED) Szelag B., ENSERG Grenoble On the transconductance enhancement at low temperature in deep submicron MOSFETs Szelag B., LPCS, ENSERG, Grenoble Hot Carrier effects and time-dependent degradation laws in 0.1µm bulk Si n-MOSFETs T --> Measurement of Channel Length and Off-set Region Length for Off-set Gate MOSFETs Tala-Ighil B., Site Universitaire Gate bias aging of unhydrogenated polycrystalline silicon TFTs Tandan N., Philips Semiconductors, Eindhoven, Netherlands A 0.5 µm Flash Technology suitable for Low Voltage Embedded Applications Tao G.Q., Philips Semiconductors, Eindhoven, Netherlands A 0.5 µm Flash Technology suitable for Low Voltage Embedded Applications Tartavel G., LETI/CEA, Grenoble Influence of thermal heating effect on pulsed DC electromigration result analysis Tauritz J.L., Delft University of Technology MAIDS: A Microwave Active Integral Device Simulator Thermal resistance modelling of RF high power bipolar transistors Tecklenburg R., Inst. of Solid State and Mat. Res., Dresden, Germany Theory and modelling of organic field effect transistors Tedesco S., LETI/CEA, Grenoble A comparative study of three designs of 0.10 µm NMOSFETs processed with heavy ion implanted pocket Terada K., Hiroshima City University --> Measurement of Channel Length and Off-set Region Length for Off-set Gate MOSFETs Thanner R., Siemens Semiconductor Division, Munich, Germany Realization and Evaluation of an Ultra Low-Voltage/Low-Power 0.25µm (n+/p+) Dual-Workfunction CMOS Technology Theunissen M.J.J., Philips Research Laboratories Technology of the Diode Programmable Read Only Memory Thim H.W., University of Linz Transferred Electron Effect in AlGaAs/GaAs Multi-Quantum-Well Structures Thomson J., GEC Plessey Semiconductors, Lincoln, UK Development of the Next Generation of Insulated Gate Bipolar Tranistors based on Trench Technology Tillack B., Institute for Semiconductor Physics CMOS Production Compatible SiGe Heteroepitaxy for High Frequency Circuits Control of steep Boron profiles in Si/SiGe heterojunction bipolar transistors Timmering C.E., Philips Research Laboratories A 34 GHz fT Bipolar Process with High-Energy-Implanted Collector Selectively-Implanted Collector Profile Optimisation for High-Speed Vertical Bipolar Transistors Tinti R., Delft University of Technology Thermal resistance modelling of RF high power bipolar transistors Toutah A., Site Universitaire Gate bias aging of unhydrogenated polycrystalline silicon TFTs Troutman W., Lucent Technologies The transistor´s discovery and what´s ahead Tsai J.-H., National Cheng-Kung University A Novel Functional Heterostructure-Emitter and Hereostructure-Base Transistor (HEHBT) Tsuji K., Hiroshima City University --> Measurement of Channel Length and Off-set Region Length for Off-set Gate MOSFETs U Slot-antenna-coupled microbolometers for far-infrared detection Udal A., Tallinn Technical University Influence of Excitonic Scattering on Charge Carrier Ambipolar Diffusion in Silicon Udrea F., University of Cambridge Development of the Next Generation of Insulated Gate Bipolar Tranistors based on Trench Technology V MAIDS: A Microwave Active Integral Device Simulator Van Calster A., Universiteit Gent A high voltage nDMOS structure in a standard sub-micron CMOS process van den Berg M.A., Philips Research Laboratories A 34 GHz fT Bipolar Process with High-Energy-Implanted Collector Van den hove L., IMEC Optical litography, how far will it get us? van den Oever L.C.M., Delft University of Technology Inverse SiGe Heterojunction Bipolar Transistor van der Hart A., Forschungszentrum Jülich --> Piezoresistive bridge configuration for atomic force microscopy van der Wel W., Philips Semiconductors, Nijmegen, Netherlands A 34 GHz fT Bipolar Process with High-Energy-Implanted Collector van Gorkum A., Philips Semiconductors, Eindhoven, Netherlands A 0.5 µm Flash Technology suitable for Low Voltage Embedded Applications van Melick N.G.H., Eindhoven University of Technology Optimization of a Lateral DMOS Transistor for Low Voltage, RF Power Operation van Ommen A., Philips Flat Panel Display Co. --> AM-LCDs bring solid-state devices to the display van Rijs F., Philips Research Laboratories, Eindhoven, Netherlands Optimization of a Lateral DMOS Transistor for Low Voltage, RF Power Operation Van Rossum M., IMEC Prospects in Silicon Nanoelectronics van Zeijl H.W., Delft University of Technology Self-aligned metallization of high-frequency BJT´s with low-stress silicon-nitride spacers Vandermoere D., IEMN-DHS A fully GaAs-based 100MHz, 2W DC-to-DC Power Converter Vanheusden K., Sandia National Lab., Albuquerque, United States Comparative hot carrier induced degradation in 0,25 µm MOSFETs with H or D passivated interfaces Varisco L., Politecnico di Milano Integrated array of avalanche photodiodes for single-photon counting Varrot M., SGS-Thomson Microelectronics, Crolles, France Effects of high temperature on performances and hot-carrier reliability in DC/AC stressed 0.35 µm n-MOSFETs Vashchenko V.A., State Research Institute "Pulsar" Simulation of avalanche injection filamentation in MOSFET's and IGBT's Microplasma and Uniform Gate Breakdown in MESFETs Velásquez J.E, Universidad de Salamanca Monte Carlo comparative study of current-mode noise in Si/Si 1-x Ge x Strained Heterojunctions Velmre E., Tallinn Technical University Influence of Excitonic Scattering on Charge Carrier Ambipolar Diffusion in Silicon Vermandel M., Universiteit Gent A high voltage nDMOS structure in a standard sub-micron CMOS process Vernet G., University Paris-South High Frequency Analysis of InP Transistors versus Temperature Verove Ch., SGS-Thomson Microelectronics 0.25 µm NMOS transistor with nitride spacer: reduction of the short channel effect by optimisation of the gate reoxidation process and reliablity Villa S., Politecnico di Milano Determination of interface state density of ULSI n-MOSFET by 1/f noise measurements Villani N., SGS-Thomson Microelectronics, Grenoble, France A Stress Technique Suitable For The In-Line Reliability Monitoring Of The Hot Carrier Endurance of Sub-0,5um MOSFETs Vinassa J.M., Université de Bordeaux I Investigations on the Internal Physical Behaviour of 600V Punch-Through IGBT under Latch-up at High Temperature Vincent G., Université Joseph Fourier, France An investigation of polysilicon emitter bipolar transistors with an ozonized polysilicon/monosilicon interface Vincent E., SGS-Thomson Microelectronics, Grenoble, France A Stress Technique Suitable For The In-Line Reliability Monitoring Of The Hot Carrier Endurance of Sub-0,5um MOSFETs Visser C.C.G., Delft University of Technology Inverse SiGe Heterojunction Bipolar Transistor Viswanathan C.R., University of California --> Mechanisms of Localized Charge Injection: A Technique to Characterize Gate Edge Damage in MOS Transistors von Philipsborn H., University of Regensburg Optimisation of Ultra High Density MOS Arrays in 3D As and B Diffusion in TiSi2/Polysilicon Gates with Dual Workfunction Gate Technology W Development of the Next Generation of Insulated Gate Bipolar Tranistors based on Trench Technology Wainwright S., Universidad del País Vasco, Bilbao, Spain The Design and Characterisation of a SiGe I²L Technology Waite A.M., University of Southampton --> An Improved Technology for Elevated Source/Drain MOSFETS Wake D., BT Laboratory, Ipswich, United Kingdom --> Analytical modeling of InP/InGaAs HBTs Waltz P., LETI/CEA, Grenoble Influence of thermal heating effect on pulsed DC electromigration result analysis Thermal analytical model for analysis of pulsed DC electromigration results Wang W.-C., National Cheng-Kung University A Novel Functional Heterostructure-Emitter and Hereostructure-Base Transistor (HEHBT) Wang F., National Semiconductor Cor. Effects of processing temperatures on device design rules for Silicon/Silicon Germanium heterojunction bipolar transistors Wanka H.N., University of Stuttgart Flexible Micro-Photodiode Array as a Subretinal Implant Warren W.L., Sandia National Lab., Albuquerque, United States Comparative hot carrier induced degradation in 0,25 µm MOSFETs with H or D passivated interfaces Weber W., Siemens Corporate Research, Munich, Germany A New Method for Verification of MOSFET Models Based on Device Parameter Variations Wehmann H.-H., Technische Universität Braunschweig --> A new cellular etching-simulator for InP and Si Werking J., SEMATECH, Austin, United States --> Mechanisms of Localized Charge Injection: A Technique to Characterize Gate Edge Damage in MOS Transistors Westergreen O., Royal Institute of Technology An InP-HBT technology for monolithic optoelectronic receivers with 24 GHz bandwidth Westrom P., National Semiconductor Cor. Effects of processing temperatures on device design rules for Silicon/Silicon Germanium heterojunction bipolar transistors Willén B., Royal Institute of Technology An InP-HBT technology for monolithic optoelectronic receivers with 24 GHz bandwidth Willer J., Siemens AG, Munich, Germany Optimisation of Ultra High Density MOS Arrays in 3D Wirth G., Fed. University of Rio Grande do Sul Periodic Transconductance Oscillations in Sub-100nm MOSFETs Woerlee P.H., Philips Research Laboratories Study of pocket implant parameters for 0,18 µm CMOS Technology of the Diode Programmable Read Only Memory Wolansky D., Institute for Semiconductor Physics CMOS Production Compatible SiGe Heteroepitaxy for High Frequency Circuits Woo J.C.S., University of California Source/Drain Engineering with Ge Large Angle Tilt Implantation and Pre-Amorphization to Improve Currrent Drive and Alleviate Floating Body Effects of Thin Film SOI MOSFETs Wu Z.Y., The University of Liverpool --> Realisation of a 0.1 µm vertical MOSFET with a SiGe source Y Investigation of the influence of impact ionization feedback on the spatial distribution of hot carriers in an NMOSFET Yamaguchi Y., Mitsubishi Electric Corporation, Hyogo, Japan Dynamic floating body effects in PD SOI MOSFETs biased in the kink region Yamamoto M., NTT Systems Electronics Labs., Kanagawa, Japan High-Frequency Small-Signal and Large-Signal Characteristics of Resonant Tunneling High Electron Mobility Transistors Yamasaki K., NTT Systems Electronics Labs. --> Novel Fabrication Technology for Ultra-Compact Three-Dimensional MMICs Yamawaki M., Mitsubishi Electric Corporation --> A Manufacturable 0.35 µm BiCMOS using Self-Aligned Cobalt SilicideTechnology Yang W., LG Semicon Co., Ltd. New anti-punchthrough design for buried channel PMOSFET Yasuoka Y., National Defense Academy Slot-antenna-coupled microbolometers for far-infrared detection Yeh J.K., Taiwan Semiconductor Manufacturing A 0.5 µm Flash Technology suitable for Low Voltage Embedded Applications Yoshino C., Toshiba Corporation Limitations of Double Polysilicon Self-Aligned Bipolar Transistor Structure Yoshitomi S., Toshiba Corporation Limitations of Double Polysilicon Self-Aligned Bipolar Transistor Structure Z HBM and CDM ESD stress test results in 0.6 µm CMOS structures Zanoni E., Università di Padova Parasitic bipolar effects leading to on-state breakdown in 2D-MESFETs Zappa F., Politecnico di Milano Integrated array of avalanche photodiodes for single-photon counting Zardini C., Université de Bordeaux I Investigations on the Internal Physical Behaviour of 600V Punch-Through IGBT under Latch-up at High Temperature Zerounian N., University Paris-South High Frequency Analysis of InP Transistors versus Temperature |