TECHNICAL PROGRAM

Tutorials by experts will provide reviews and updates of selected topics of actual interest. Invited papers (pdf file) will introduce the main stream topics.

Session A : Reliability and Lifetime Prediction / Wafer Level Reliability

Session B : Detection and Modelling of Failure mechanisms : Oxide, ESD

Session C : EOBT - Electron and Optical Beam Testing

Session D : Advanced Failure Analysis : case studies

Session E : Reliability of Compound Semiconductors

Session F : Reliability of interconnections, Packaging and MEMS

Session G : Reliability of Power Devices

A synthetic schedule is available under pdf format file.

Tutorials	Session A1/A2	Session F	Session D	EOBT
Session B1/E1	Session E2/B2	Session F2	Session G	Posters

Tuesday, October 2, morning

(Main Auditorium)

8:00 Registration

9:00 Official Opening of ESREF 2001

Best Paper AWARDS of ESREF 2000

Chairman : A. TOUBOUL (IXL, University of Bordeaux - France)

9:30 Tutorial

Chairman : A. Mouthaan (University of Twente - The Netherlands)

T1 Reliability Simulation for DSM full-chip Integrated Circuits

Lifeng Wu, Zhihong Liu (Celestry Design Technologies - USA)

As the transistor channel length scales down toward 0.1 micron and new processes loom ahead, circuit reliability simulation technologies should be on the finger-tips of the circuit designers to maximize design performance by minimizing design guard-band, to speed-up timing closure by reducing design iterations and to ensure long-term circuit reliability. Most common circuit reliability issues such as hot-carrier effect and electromigration are discussed in this tutorial as an alternative to TD fix of those issues. It has been shown that although the simulation flow has no obvious change in VDSM era and for new processes such as SOI, thin dielectric film and copper interconnect, more degradation mechanisms need to be investigated and more modeling issues need to be solved in the simulation procedure. Both full-chip transistor-level and cell-based solutions should be provided for circuit designers with million-transistor/million-gate capacity and Spice-accuracy. Reliability simulation constitutes one of the key roles in the full-chip design silicon-accuracy sign-off flow, as well as the parasitic extraction, coupling noise timing analysis and power grid IR drop.

11:00 Coffee break

11:30 Tutorial

Chairman : O. Bonnaud (University of Rennes - France)

T2    From 0.18µm to 0.10µm Technology: A Blend of Evolution and Revolution

Fabio Pintchovsky (MOTOROLA - USA)

The semiconductor industry is unique in having sustained such rapid technology development over so long a period. This has enabled the industry to provide electronic products with substantially lower cost per function as well as higher performance each year. In this talk entitled "From 0.18µ to 0.10µ Technology: A Blend of Evolution and Revolution", integrated circuit technology characteristics required to maintain the historical rate of performance and cost improvements will be discussed. Those will include the areas of transistor engineering, oxide scaling, advanced interconnect systems and reliability.

13:00 Lunch

Tuesday, October 2, afternoon

(Main Auditorium)

14:30 Tutorial

Chairman : L.J. Balk (University of Wuppertal – Germany)

T3     Scanning Probe Microscopy Techniques for Failure Analysis of Microelectronic Devices – Fundamentals and Applications

W. Mertin, E. Kubalek (Gerhard-Mercator-Universität Duisburg - Germany)

While the original applications of scanning probe microscopy (SPM) concentrated on nano scale surface investigation, a variety of applications suitable for the study of semiconductor properties and IC operation, and for IC failure localization has been developed in the last few years. The tutorial will start with reviewing the basic principles of SPM techniques and their corresponding equipment. Then it will demonstrate several advanced applications in the field which are of current interest in failure analysis of microelectronic devices, e.g. scanning capacitance microscopy, scanning thermal microscopy, scanning probe voltage and scanning probe current measurements.

16:00 Coffee break

16:30   Tutorial

Chairman : P. Leblanc (ASTRIUM – France)

T4    Reliability improvements in passive components

P.O. Fagerholt (CLR Consult -Sweden)

A number of different measures taken on actual components can remarkably improve their reliability in operation. Such actions described are derating of:

· working dc voltage (remarkable example with solid tantalums),

· temperature by choosing styles with low ESR (solid Ta),

· maximum manufactured values (film resistors, ceramic chip capacitors),

· different wiper current accommodations in wire wound and non-wire wound potentiometers,

· exemplified burn in treatments, on solid Ta, NTC thermistors and film capacitors,

· choosing right designs (film capacitors subjected to high voltage rise times),

· precautions concerning wet aluminium electrolytics subjected to halogenated washing agents, and short power pulses applied on metal oxide resistors with films on glass rods,

· some application precautions (NTC and PTC thermistors, ceramic class 2 capacitors).

18:00 Cocktail offered by Equipment Exhibitors

PROGRAM HIGHLIGHTS

Wednesday, October 3, morning

(Main Auditorium)

Session A1 : Reliability and Lifetime Prediction

Chairman : A. Touboul (IXL, University of Bordeaux - France)

8:30 Invited Conference

IP1 About the 300 mm implementation strategy at ST Microelectronics

J. Hartmann (ST Microelectronics – France)

9:10   A1  An extrapolation model for lifetime prediction for off-state-degradation of MOSFETs

A. Muehlhoff (Infineon AG – Germany)

9:30   A2  Determination of dielectric breakdown Weibull distribution parameters confidence bounds for accurate ultrathin oxide reliability predictions

F. Monsieur^1.2, E. Vincent¹, D. Roy¹, S. Bruyere¹, G. Pananakakis², G. Ghibaudo² (¹STMicroelectronics - France, ²LPCS/ENSERG -France)

9:50   A3  Analysis of retention tail distribution induced by scaled shallow trench isolation for high density DRAMs

Y. Pil Kim, B.J. Jin, Y. W. Park, J.T. Moon, S.U. Kim (Samsung Electronics.- Korea)

10:10  A4  Hot-carrier reliability for Si and SiGe HBTs: Aging procedure, extrapolation model : limitations and applications

X. Garros, N. Revil (STMicroelectronics – France)

10:30 Coffee break

Session A2 : Wafer Level Reliability

Chairmen : G. Deleuze (EDF - France)

J. Möltoft (Orsted.DTU, Technical University - Denmark)

10:50 Invited Conference

IP3  From space to ground : Soft error rate (SER) in commercial microelectronic devices

Ph. Calvel (ALCATEL Espace – France), J. Gasiot (CEM - University of Montpellier - France)

11:30  A5  Substrate engineering to improve soft-error-rate immunity for SRAM technology

H. Puchner, Y.C. Liu, W. Kong, F. Duan, R. Castagnetti (LSI Logic Corp. - USA)

11:50  A6  Improved stability of large area excimer laser crystallised polysilicon thin film transistors under DC and AC operating

H. Toutah¹, J.F. Llibre¹, B. Tata-Ighil¹, T. Mohammed-Brahim², Y. Helen², G. Gautier², O. Bonnaud² (¹LUSAC, ²University of Rennes 1 – France)

12:10  A7  Wafer Level Accelerated test for ionic contamination control on VDMOS transistors in Bipolar/CMOS/DMOS technology

Y. Rey-Tauriac1,2, M. Taurin2, O. Bonnaud2 (1Université de Rennes, 2STMicroelectronics – France)

12:30 Lunch

PROGRAM HIGHLIGHTS

Wednesday, October 3, afternoon

(Main Auditorium)

Session F : Reliability of Interconnections and Packaging

Chairman : J. Bisschop (Philips - The Netherlands)

14:00  Invited Conference

IP7  Effects of temperature and humidity on the reliability of interfaces in microelectronic devices

Michael Lane (IBM TJ Watson Research Center- USA)

14:40  F1  Three dimensional simulation of voids formation in chip-level metallization structures : A contribution to reliability evaluation

D. Dalleau, K.Weide-Zaage (Universität Hannover - Germany)

15:00  F2  Reliability studies on multilevel interconnection with inter-metal dielectric air gaps

V. Sukharev, B. Sheih, R. Choudhury¹, C. Park (LSI Logic Corp, ¹University of Stanford - USA)

15:20  F3  Stress modelling of multi level interconnect schemes for future deep submicron device generations

C.G. Montes de Oca¹, S. Foley², A. Mathewson³ (¹Baltimore Technologies, ²Cypress Semiconductors, ³NMRC – Ireland)

15:40 Coffee break

Session F : Reliability of Interconnections and Packaging

Chairman : Y. Danto (IXL, University of Bordeaux - France)

16:00  Invited Conference

IP8  The connection between thermal and mechanical stresses in BGA component reliability testing

Michel Ignat (INPG-ENSERG- France)

16:40  F4  Thermal fatigue in solder joints of Ag-Pd  and Ag-Pt metallized LTCC modules

R. Rautioaho, O. Nousiainen, S. Leppävuori, J. Lenkkeri, T. Jaakola (University of Oulu – Finland)

17:00  F5  RF packaging for microwave applications : from micropackage to SOP, "System On a Package"

C. Drevon (ALCATEL Space Industries - France)

17:20 Workshop : “Reliability and Electronic Interfaces”

Moderators : R.W. Thomas (Technology Expert Network - USA)

Y. Danto (IXL, University of Bordeaux - France)

19:00 End of sessions

PROGRAM HIGHLIGHTS

Wednesday, October 3, afternoon

(Parallel sessions in room 3.5, third floor

Session D : Advanced Failure Analysis : case studies

Chairman : Ph. Perdu (CNES - France)

M. Vanzi (University of Cagliari – Italy)

10:50  Invited Conference

IP4  Characterization of process induced defects

Kasuko Ikeda (NEC Corp. - Japan)

11:30  D1  A reliable course of scanning capacitance microscopy analysis applied for 2D‑Dopant profilings of power MOSFET devices

M. Leicht¹, G. Fritzer¹, B. Basnar², S. Golka², J. Smoliner² (¹Infineon Technologies, ²TU Wien - Austria)

11:50  D2  Backside localization of current leakage faults using thermal laser stimulation

R. Desplat¹, F. Beaudoin¹, Ph. Perdu¹, D. Lewis² (¹CNES, ²University of Bordeaux – France)

12:10  D3  Reliability of ultra thinning C4 integrated circuits for backside analysis

E. Delenia, C.C. Tsao (Schlumberger – USA)

PROGRAM HIGHLIGHTS

12:30 Lunch

Session C : EOBT - Electron and Optical Beam Testing

Chairmen : R. Cramer (ALTIS Semiconductor - France)

W. Claeys (CPMOH, University of Bordeaux - France)

14:00  Invited Conference

IP5  Scanning probe microscopy in semiconductor failure analysis

B. Ebersberger, A. Olbrich, C. Boit (Infineon - Germany)

14:40  C1  Diamond-coated cantilevers for scanning capacitance microscopy applications

H. Yabuhara¹, M. Ciappa², W. Fichtner² (¹Toshiba - Japan, ETH Zürich - Switzerland)

15:00  C2  Why hot carrier emission probes such as PICA will work for 50 nm, 1V CMOS technologies

J.C. Tsang, M.V. Fischetti (IBM T.J. Watson Research Center - USA)

15:20  C3  Backside and front side picosecond OBIC mapping on ICs, Application for single event transient studies

D. Lewis¹, V. Pouget², T. Beauchene¹, H. Lapuyade¹, A. Touboul¹, F. Beaudoin¹, P. Perdu² (¹IXL, University of Bordeaux; ²CNES ‑ France)

15:40  C4  Modeling thermal laser simulation

F. Beaudoin¹, X. Chauffeur², J.P. Fradin², Ph. Perdu¹, R. Desplats¹, D. Lewis³ (¹CNES -Thales, ²Epsilon Ingenierie, ³IXL, University of Bordeaux - France)

16:00 C5  Coaxial ion-photon dual beam system

C.C. Tsao¹, L. Madison¹, P. Bouchet², P. Sudraud² (¹Schlumberger - USA, ²Orsay Physics - France)

16:20 Coffee break

16:40 to 19:00  Workshop : “European Failure Analysis Network”

Moderators : Ch. Boit (Infineon Technologies- Germany)

Ph. Perdu (CNES - France)

PROGRAM HIGHLIGHTS

Thursday, October 4, morning

(Main Auditorium)

Session B1 : Detection and Modelling of Failure mechanisms: Oxide Reliability

Chairman : N. Stojadinovic (University of Nis - Yugoslavia)

G. Ghibaudo (LPCS/ENSERG – France)

8:30    Invited Conference

IP2  Anode hole generation mechanisms

Andrea Ghetti (ST Microelectronics – Italy), Muhammad A. Alam,Jeff Bude (Agere Systems – USA)

9:10   B1-1  Creation and thermal annealing of interface states induced by uniform and localized injections in 2.3nm thick oxides

D. Zander, F. Saigné, A. Meinertzhagen (LAM, University of Reims – France)

9:30   B1-2  Low frequency noise and reliability properties of 0.12µm CMOS devices with Ta2O5 as gate dielectrics

M. Fadlallah¹, A. Szewczyk¹, C. Giannakopoulos^1,2, B. Cretu¹, F. Monsieur^1,2, T. Devoivre², J. Jomaah¹, G. Ghibaudo¹ (¹LPCS/ENSERG, ²STMicroelectronics – France)

9:50   B1-3  Failure in ultrathin oxides : Stored energy or carrier energy driven ?

S. Bruyere¹, F. Monsieur^1,2, D. Roy¹, E. Vincent¹, G. Ghibaudo² (¹STMicroelectronics, ²LPCS/ENSERG – France)

10:10  B1-4  Mechanisms of positive gate bias stress induced instabilities in power VDMOSFETs

N. Stojadinovic, I. Manic, S. Djoric-Veljkovic, V. Davidovic, S. Golubovic, S. Dimitrijev (University of Nis – Yugoslasvia)

10:30 Coffee break

Session E1 : Reliability of Compound Semiconductors

Chairman : J.M. Dumas (ENSIL, University of Limoges – France)

F. Garat (ESTEC/ESA – The Netherlands)

10:50  Invited Conference

IP6  Technological limits associated with the introduction of InP high speed electron devices into fiber optic systems

A. Scavennec (OPTO+ - France)

11:30  E1-1  Defect detection and modelling using pulsed electrical stress for reliability investigations of InGaP HBT

C. Sydlo¹, B. Mottet¹, H. Ganis², H.L. Hartnagel¹, V. Krozer², S. Delage³, S. Cassette³, E. Chartier³, D. Floriot³, S. Bland⁴ (¹TU Darmstadt,^{, 2}TU Chemnitz‑Germany, ³Thomson CSF LCR-France,⁴IQE-UK)

11:50  E1-2  Evolution of LF noise in power PHEMT submitted to RF and DC life-tests

B. Lambert¹, N. Labat¹, N. Malbert¹, F. Verdier¹, A. Touboul¹, P. Huguet², R. Bonnet², G. Pataut² (¹IXL, University Bordeaux 1, ²United Monolithic Semiconductors – France)

12:10 E1-3  Long term stability of InGaAs/AlInAs/GaAs metamorphic HEMTs

G. Meneghesso, A. Chini, E. Zanoni (Universita di Padova – Italy)

12:30 E1-4  Gate-lag effects in AlGaAs/GaAs power HFET's

E. Tediosi¹, M. Borgarino¹, G. Sozzi², G. Verzellesi¹ (¹Universita' di Modena e Reggio Emilia, ²Universita" di Parma- Italy)

12:50 Lunch

PROGRAM HIGHLIGHTS

Thursday, October 4, morning

(Parallel sessions in room 3.5, third floor)

Session E2 : Reliability of Compound Semiconductors

Chairman : H.L. Hartnagel (Technical University of Darmstadt – Germany)

J.M. Dumas (ENSIL, University of Limoges – France)

9:10   E2-1  A refined method to measure the thermal resistance of heterojunction bipolar transistors under high-power conditions

R. Petersen¹, W. De Ceuninck¹, L. De Schepper¹, O. Vendier², H. Blanck³, D. Pons³ (¹Limburgs University Centre – Belgium, ²ALCATEL Space - France, ³United Monolithic Semiconductors - Germany)

9:30   E2-2  Laser diode COFD analysis by thermoreflectance microscopy

S. Dilhaire, S. Grauby, S. Jorez, L.D. Patino Lopez, E. Schaub, W. Claeys (CPMOH, University of Bordeaux – France)

9:50   E2-3  Damp heat test on LiNbO optical modulators

P. Furcas¹, R. De Palo¹, M.E. Patella¹, G. Salmini¹, M. Vanzi² (¹Cisco Photonics, ²University of Cagliari– Italy)

10:10  E2-4  Investigation on ESD-stressed GaN/InGaN-on-sapphire blue LEDs

G. Meneghesso¹, S. Podda², M. Vanzi² (¹University of Padova,²University of Cagliari– Italy)

10:30 Coffee break

Session B2 : Detection and Modelling of Failure Mechanisms: ESD

Chairman : N. Stojadinovic (University of Nis - Yugoslavia)

G. Ghibaudo (LPCS/ENSERG – France)

10:50  B2-1  ESD-induced circuit performance degradation in RFICs

K. Gong, H. Feng, R. Zhan A. Z. Wang (Illinois Institute of Technology – USA

11:10  B2-2  Effect of pulse risetime on trigger homogeneity in single finger grounded gate nMOSFET electrostatic discharge protection devices

M. Litzenberger¹, R.Pichler¹, S. Bychikhin¹, D. Pogany¹, K. Esmak²,H. Gossner², E. Gornik¹ (¹TU Vienna – Austria, ²Infineon Technologies ‑ Germany)

11:30  B2-3  The time-voltage trade-off for ESD damage threshold in amorphous silicon hydrogenated thin-film transistors

N. Tosic¹, S. vanderWal², F.G. Kuper^3,1, T. Mouthaan¹ (¹University of Twente, ³Philips Semiconductors - The Netherlands, ²Philips Semiconductors - UK)

11:50  B2-4  Relevance of contact reliability in HBM-ESD test equipment

J.C. Reiner, T. Keller (Philips Semiconductors – Switzerland)

12:10  B2-5  Non contact surface potential measurements for charging reduction during manufacturing of metal-insulator-metal capacitors

J. Ackaert¹, I.Z. Wang², E. De Backer¹, P. Colson1, P. Coppens¹ (¹Alcatel Microelectronics – Belgium, ²MESA+, University of Twente – The Netherlands)

12:30 Lunch

PROGRAM HIGHLIGHTS

Thursday, October 4, afternoon

(Main Auditorium)

Session F2 : Reliability of interconnections and MEMS

Chairman : E. Wolfgang (Siemens, Germany)

14:00  Best paper award of RCJ 2000 conference (invited)

Electromigration performance of multi-level damascene copper interconnects

S. Yokogawa, N. Okada, Y. Yakuhara, H. Takizawa (NEC Electron Devices – Japan)

14:20  Best paper award of IRPS 2001 conference (invited)

IP.IRPS to be confirmed

14:40  Best paper award of IPFA 2001 conference (invited)

IP.IPFA to be confirmed

15:00  F6  Mechanical reliability of MEMS-structures under shock-load

U. Wagner¹, J. Franz¹, M. Schweiker¹, W. Bernhard¹, R. Müller-Fiedler¹, B. Michel² (¹Robert BOSCH, ²Fraunhofer Institute IZM Berlin - Germany)

15:20 to17:00    Parallel sessions

(Lobby, second floor) Poster Session

(Room 3.5, third floor) Workshop :“Reliability in Automotive Power Electronics”

Moderators : E. Wolfgang (Siemens - Germany) and M. Ciappa (ETH Zürich - Switzerland)

PROGRAM HIGHLIGHTS

17:30 Bus departure to the gala dinner

Friday October 5

(Main Auditorium)

Session G : Reliability of Power Devices

Chairman : M. Ciappa (ETH Zürich – Switzerland)

W. Wondrak (DaimlerChrysler - Germany)

9:00   Invited Conference

IP9  Thermal management and reliability of multichip power modules

Guy Lefranc (SIEMENS - Germany)

9:40   G-1  Integrated power transistor size optimisation

J.M. Bosc (Motorola Toulouse – France)

10:00  G-2  Operation of power semiconductors under transient thermal conditions: thermal fatigue reliability and mechanical aspects

S. Forster^1,2, T. Lequeu¹, R. Jerisian¹ (¹LMP-STMicroelectronics, ²CLOES – France)

10:20  G-3  ESD protection structures for BCD5 smart power technologies

L. Sponton¹, L. Cerati¹, G. Croce¹, F. Chrappan¹, C. Contiero¹, G. Meneghesso², E. Zanoni² (¹ST Microelectronics, ²Universita di Padova – Italy)

10:40  G-4  Reliability of non-hermetic pressure contact IGBT modules

F. Richter, E. Herr, R. Schlegel (ABB Semiconductors – Switzerland)

11:00 G-5  Power module lifetime estimation from chip temperature direct measurement in an automotive traction inverter

G. Coquery¹, S. Carubelli¹, J.P. Ousten¹, R. Lallemand¹, F. Lecoq², Ph. Dupuy² (¹INRETS - ²Renault -France)

11:20  G-6  A pragmatic methodology for the monitoring of the electronic components ageing :The case of power thyristors at EDF

G. Guffroy, G. Simon (EDF R&D - France)

11:40   Announcement of ESREF 2001 Best Paper Awards

12:00   Conference closing

13:30  Bus departure to Bordeaux Mérignac International Airport

PROGRAM HIGHLIGHTS

POSTERS

Session A : Quality and Reliability Implementation

AP1   Reliability of polycrystalline silicon thin film resistors

M. Nakabayashi¹, H. Ohyama², E. Simoen³, M. Ikegami¹, C. Claeys^3,4, K. Kobayashi², M. Yoneoka², K. Miyahara⁵ (1Mitsubishi Electric Co, ²Kumamoto National College of Technology, ⁵Kumammoto University – Japan, ³IMEC, ⁴KU Leuven - Belgium)

AP2   Injection mechanisms and lifetime prediction with the substrate voltage in 0.15µm channel-length N-MOSFET's

A. Bravaix¹, D. Goguenheim¹, N. Revil², E. Vincent² (¹L2MP-ISEM, ²STMicroelectronics – France)

AP3   Polysilicon oxide quality optimization at wafer level of a bipolar/CMOS/DMOS technology

X. Gagnard^1,2, Y. Rey-Tauriac^1,2, O. Bonnaud¹ (¹Université de Rennes 1, ²STMicroelectronics – France)

Session B : Detection and Modelling of Failure Mechanisms

BP1   An overview of hot-carrier induced degradation in 0.25 µm partially & fully depleted SOI N-MOSFET’s

F. Dieudonne¹, F. Daugé¹, J. Jomaah¹, C. Raynaud², F. Balestra¹ (¹LPCS/ENSERG, ²CEA/LETI – France)

BP2   Stress induced leakage current at low field in ultra thin oxides

F. Lime¹, G. Ghibaudo¹, G. Guégan² (¹ENSERG, ²CEA/ LETI – France)

BP3   Electric annealing of interface traps at drain space charge region in p-MOSFET’s

G.Chen¹, M.F. LI¹, Y. Jin² (¹CICFAR, ²Chartered Semiconductor Manufacturing - Singapore)

BP4   Simulation and experimental comparison of GGNMOS and LVTSCR protection cells under electrostatic discharges

A. Guilhaume^1,2, P. Galy³, B. Foucher¹, I. Lombaert-Valot¹, S. Bardy⁴, J.P. Chante² (¹EADS CCR, ²CEGELY, ³Pôle Universitaire de Vinci, ⁴Philips Semiconducteurs – France)

BP5   High-resolution in-situ study of gold electromigration test time reduction

K. Croes¹, R. Dreesen¹, J. Manca¹, W. De Ceuninck¹, L. De Schepper¹, L. Tielemans², P. Van Der Wel³ (1Limburgs University Centre, ²Xpeqt – Belgium, ³Philips Semiconductors - The Netherlands)

BP6   Degradation of npn Si transistors by high-temperature gamma ray and electron irradiation

H. Ohyama¹, T. Hiroa2, E. Simoen³, C. Claeys^3,4, Y. Fukushima1, A. Tanigawa¹, M. Nakabayashi⁵, S. Onoda⁶ (¹Kumamoto National College of Technology, ²Takasaki JAERI, ⁵Mitsubishi Electric Co, ⁶Tokai University - Japan, ³IMEC, ⁴KU Leuven - Belgium)

Session C : EOBT - Electron and Optical Beam Testing

CP1   Development of an EB/FIB integrated test system

K. Miura, K. Nakamae, H. Fujioka (Osaka University – Japan)

CP2   A new versatile testing interface for failure analysis in integrated circuits

R. Desplat, Ph. Perdu, F. Beaudoin (CNES-SOREP – France)

CP3   Thermal and free carrier laser interferometric mapping and failure analysis of anti-serial smart power ESD protection structures

S. Bychikhin, M. Litzenberger, R. Pichler, D. Pogany, E. Gornik (Vienna University of Technology – Austria)

CP4   Unique and practical IC timing analysis tool utilizing intrinsic photon emission

N. Goldblatt, G. Dajee, S. Somani (Schlumberger Probe Systems – USA)

CP5   Theoretical investigation of an equivalent laser LET

V. Pouget¹, H. Lapuyade¹, P. Fouillat¹, D. Lewis¹, S. Buchner² (¹University Bordeaux – France, ²SFA. - USA)

CP6   Analysis of high-power devices using proton beam induced charge microscopy

M. Zmeck^1,2,3, J.C.H. Phang¹, A; Bettiol, T. Osipowicz², F. Watt², L.J. Balk³, F.J. Niedernostheide⁴, H.J. Schulze⁴, E. Falck⁵, R. Barthelmess⁵ (¹Faculty of Engineering, KentRidge, ²National University of Singapore - Singapore, ³Universität Wuppertal,⁴Infineon, ⁵Eupec - Germany)

Session D : Advanced Failure Analysis : case studies

DP1   A novel application of the FIB lift-out technique for 3-D TEM analysis

J.C. Lee, D. Su (TSMC - Taiwan)

DP2   Silicon thinning and polishing on packaged devices

F. Beaudoin, Ph. Perdu, R. Desplats (CNES - France)

Session G : Power devices

GP1   High reliability power VDMOS transistors in bipolar/CMOS/DMOS technology

Y. Rey-Tauriac^1,2, M. Taurin¹, O. Bonnaud²(¹ST Microelectronics, ²University of Rennes – France)

GP2   A novel power module design and technology for improved power cycling capability

U. Scheuermann (Semikron Elektronik – Germany)

GP3   Reliability of chip DCB solder joints in AlSiC base plate power modules : influence of chip size

M. Thoben¹, X. Xie², D. Silber³ (¹DaimlerChrysler, ³University of Bremen– Germany, ²SIM-DaimlerChrysler - China)

GP4   Non-destructive tester for single event burnout of power diodes

G. Busatto, F. Iannuzzo (Universita degli Studi di Cassino - Italy)

GP5   Local lifetime control IGBT structures : Turn-off performances comparison for hard- and soft-switching between 1200V trench PT- and new planar PT-IGBTs

S. Azzopardi¹, A. Kawamura, H. Iwamoto (¹IXL, University of Bordeaux - France)

PROGRAM HIGHLIGHTS

WELCOME ESREF 2001