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Properties of crystalline siliconEdited by Robert Hull, University of Virginia, USA |
Chemical etchstop technology [1,2] represents a powerful approach to thinning bonded SOI structures in order to obtain thin Si layers with extremely low tolerances [3,4,5]. The technology uses a chemical etch to remove material from the device wafer side of the bonded wafer structure which is designed so that the etch rate decreases by several orders of magnitude when reaching the etchstop layer. Thus, a device layer can be produced without having to rely solely on mechanical grind and polish steps to reach the target thickness. This approach is known as the bond and etchback ("BESOI") approach to SOI. Possible choices for the combination of etch stop layer and etching chemistry [2] are listed in TABLE 1. To produce SOI with this technology, the etchstop layer is, in general, created in the device wafer prior to bonding either by epitaxial or ion implantation techniques at a certain depth which in turn determines the final device layer thickness. >From the viewpoint of manufacturability, epitaxy appears to be superior to ion implantation for producing etchstop layers in terms of efficiency and residual defect density.[5] Use of the epitaxial approach has the added advantage that the final Si device layer is formed from epitaxial material instead of CZ or FZ Si which is of higher crystal quality in terms defects and impurity concentration.
The most important advantage of BESOI over the bond and grindback process is that the thickness variation of the handle wafer is not a critical factor in determining the thickness variation of the SOI device layer. There are currently two major variations of the etchstop technology, single and double etchstop, which are discussed below in more detail. Common to both approaches is a room temperature joining process followed by a high temperature anneal to strengthen the bonding. The maximum bonding temperature is determined by the requirement to maintain the integrity of the epitaxial etchstop layer. The etchstop layer integrity can be affected by too high temperatures in the several ways: (a) contamination of the low doped device layer because of diffusion; (b) loss of a well defined etch stop layer; and (c) precipitation or deactiviation of the solute dopant resulting in a loss of etch selectivity [32] .To use the etchstop technology in an efficient manner, the device wafer is typically thinned via grind and polish back to a thickness within several tens of µm of the location of the etchstop so that chemical etching is employed only for removing the remaining, relatively thin layer of material above the etchstop.
The single etchstop approach to BESOI [4, 49] uses a p or n-type epi layer on a p+ substrate as the starting point where the etching chemistry is designed to stop at the transition from p+ to the lower doped layer. The device layer thickness achievable with this approach is between 0.5 and 50µm with a total thickness variation (TTV) of 10 % or better. The device epi wafer consists of a low doped p or n type layer grown on a p+ epi substrate. This structure is a standard part used in CMOS-type applications and is widely available commercially in high quality. The maximum achievable device layer thickness has a practical limit determined by the quality and cost of very thick epitaxial layers.
The chemical etchant used in the single etchstop process is based on hydrofluoric acid, nitric acid and acetic acid (HNA) and requires that the doping of the epi substrate wafer is sufficiently high, in the range of 1x1018-3x1020cm-3. The buried oxide layer is typically grown on the handle wafer but can also be grown on the epitaxial structure serving as the device wafer. The handle and the device wafer are joined at room temperature and then are annealed at high temperature. In the subsequent thinning process, the bulk of the device wafer is removed via grinding and polishing. The polishing step is designed so that any surface damage is removed and a surface roughness of Ra < 10Å is attained. After the structure has been thinned to 5-15µm above the etchstop, the chemical etching process is initiated by immersing the wafer into the etch bath. The etchant consists of HF-HNO3-CH3COOH at a concentration of about (1:3:8) together with a surfactant to improve etching performance. The temperature of the bath is kept between 20° and 30 °C. The initial etch rate of 0.2-2 µm/min typically decreases with time and will eventually lead to cessation of the etching process due to autocatalytic poisioning of the etchant. The etching process can be restarted by the addition of oxidizing chemicals (ozone, H2O2 ) to the etch bath or by exposing the etched Si surface to air. Upon reaching the etchstop transition, etching action cannot be reactivated and the wafer is subjected to a ‘touch polish’ process in which 0.2-0.5µm of Si are removed through polishing to eliminate the residual boron tail on the surface of the device layer and to obtain the surface roughness comparable to a polished wafer.
Using the single etchstop SOI process, a total thickness variation of 0.7 µm or better can be achieved easily on production quantity lot sizes for a given thickness target in the range of 1-20 µm (see FIGURE 1). For more demanding applications, the uniformity can be improved through process optimization to yield a TTV of 0.2 µm for layers up to 2 µm thickness (see FIGURE 2).
The double etchstop approach to BESOI is used to produce ultrathin SOI (0.01 µm dtSid 1µm) with very low tolerances. The device wafer consists of a two layer epi structure deposited on a lightly or undoped epi substrate. The first layer deposited on the epi substrate is the etchstop, a very thin (t<0.5 µm) but highly boron (p) doped (> 1x1019 cm-3) layer, and the second layer, grown on top of the p+ layer, is lightly doped and will become the SOI device layer. The highly doped etchstop layer is typically codoped with germanium to compensate the lattice strain associated by the high boron concentration (see FIGURE 3).
Strain compensation prevents the propagation of misfit dislocations into the device layer[5].The technical realization of the double etch stop epi structure requires the use of advanced expitaxial techniques [32]. Low temperature epi growth processes (Tgrowth< 1000°C) have been used to obtain high quality epi layers with very sharp doping transitions (< a few nm) between the etchstop and the device layer as required to achieve the desired thickness control and low background doping of the device layer. The requirement to maintain the integrity of the etchstop layer until the etchback step in the manufacturing process imposes a limitation on the annealing temperature of the bonded wafer pair prior to thinning to temperatures less than the epi growth temperature. In addition to very sharp doping transitions, this process requires extremely clean and particulate and defect free bonding surfaces in order to produce high quality ultra thin SOI. This requirement is very important because the strain field around a particulate located at the bonding interface can cause enhanced reactivity during the etching process, giving rise to blisters or voids in the device layer much larger than the size of the particulate.
The undoped part of the device wafer is removed by an etching solution which stops at the p+ etchstop layer such as ethylenediamine-pyrocatechol-water (EPW) etch solution [67] or KOH [4]. With the EPW chemistry, etch rates of 10-50µm/h are typically achieved on low doped material. The sacrifical p+ etchstop layer, in turn, is removed by a second etching step based on the HF-HNO3-CH3COOH (HNA) chemistry which is designed to stop at the p+ to p transition. Using the combination of EPW and HNA, the combined selectivity of the two etching steps in greater than 104 so that the final layer uniformity is determined by the tolerances of the epi growth process.
After the etchback process, a thin layer of relatively boron rich material (see FIGURE 4) is left on the surface of the device layer. This layer with a thickness of a few hundred Ångstroms is the tail of the boron etchstop layer not removed by the etchant. To remove the boron tail, a light polishing step (kiss polish) [68] is employed which also produces a surface roughness comparable to a polished bulk wafer. A key consideration in designing this polish process is the necessity to minimize the TTV degradation associated with polishing. At a removal of approximately 0.035µm, the "kiss" polish can be optimized to result in a TTV degradation (FIGURE 5) of less than 0.01 µm while achieving a surface roughness of Ra = 1 Å. For finished product SOI wafers at a nominal device layer thickness of 0.2µm, the thickness variation on each wafer is typically less than 0.007µm (standard deviation) and the average layer thickness falls into a range of less than 0.01µm (FIGURE 6).
The issue of metallic contamination is critical to SOI, more so for ultra-thin layers that are usually fabricated using the double etchstop technique. Metallic contamination may occur during processing of the SOI layer from a variety of sources including epitaxial growth and buried oxide growth. Unlike the case of Simox, BESOI layers do not have extensive defects structures on the substrate side of the buried oxide to getter these impurities. As a result, these impurities will find their way in some concentration in the superficial Si layer. Thermal processing will usually leave the metal complexed with silicon. Besides the deleterious effect that such impurities may have on recombination lifetime, they are a source of the so-called HF defect. When subjected to concentrated HF action, the metal complex (usually a silicide) is preferentially etched and a microcapilary results, exposing the buried oxide to the effects of the HF. As the buried oxides etches rapidly and isotropically, a blister is formed as shown in FIGURE 7. Early BESOI samples from all manufacturers had up to 104 cm-2 such HF defects. HF defects can be a major yield detractor for further IC processing especially epi growth. However, attention to established ultraclean semiconductor processes and good manufacturing control have reduced the defect levels to well below 10 cm-2 and HF defects are no longer considered an issue but remain a very sensitive metric of metallic contamination in all SOI without built-in gettering layers.
Chemical etchstop technology is a powerful approach to producing SOI layers between 0.01 and approx. 20 µm with extremely low TTV, thereby opening thickness ranges and applications not accessible to the conventional bond and grindback approach to SOI. The use of epitaxially grown etchstop layers also implies that in the final SOI structure, the active Si device layer is formed from epitaxially grown material which is advantageous in some device applications.
Weaknesses of the BESOI approach might perhaps be found in limitations to the maximum bonding anneal temperature in order to preserve the integrity of the etchstop and susceptibility of the final SOI layer to defects resulting from the epi growth process.
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Etch Stops for Silicon | |||
|
Etchstop Layer |
Etched Material |
Etchant |
Reference |
|
Heavily doped etch stop layers | |||
|
p+ Si (Boron) |
n- and p- Si |
KOH, EDP, Hydrazine |
|
|
p+ Si (Gallium) |
n- and p- Si |
KOH |
|
|
p+ Si (P, As, Sb) |
p- and n- Si |
KOH |
|
|
Strain compensated | |||
|
p + Si (Boron) Sn added for strain compensation |
p Si or n- Si |
EDP |
|
|
p + Si (Boron) Ge added for strain compensation |
p Si or n- Si |
KOH, EDP |
|
|
Germanium doped | |||
|
Si/Ge |
Si |
EDP,KOH(/K2CrO7) |
|
|
Displacement Reaction Etch Stop | |||
|
n= Si Si |
n- and p- Si porous Si |
WF6(Gaseous) KOH HNA |
|
|
Lightly doped Etchstop layers | |||
|
n or p Si (lightly doped) SixGey |
n+ or p+ Si (heav. dop.) Si |
HF/HNO3/HAc KOH/K2CrO |
|
|
Ion implanted etch stops | |||
|
Oxygen implantation | |||
|
SiO2 (SiOx) |
Silicon (n- or p-type) |
KOH,EDP |
|
|
Nitrogen implantation | |||
|
Si3N4 (SixNy) |
Silicon (n- or p-type) |
KOH, EDP,TMAH |
|
|
Carbon implantation | |||
|
SiC (SiCx) |
Silicon (n- or p-type) |
KOH, EDP |
|
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Germanium implantation | |||
|
Si/Ge > 5% |
Si |
EDP |
|
|
Boron implantation | |||
|
p Si (>1019 cm-3) |
p, n , n+ Si |
KOH, NaOH,EDP |
|
|
Hydrogen implantation | |||
|
n-type Silicon |
p-type Silicon |
HF/anodic potentials |
|
|
Implantation damaged |
|||
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Damaged Areas Implanted Species P, Ge, C, Si, Electrons B,H, Ne, P |
Undamaged Areas Substrate: Si Si |
KOH/EDP HF/anodic potentials |
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The above Datareview is an expanded version of 18.5 in the book Properties of crystalline silicon.edited by Robert Hull (University of Virginia).
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