The 2001 IRPS Tutorials program is designed to maximize attendees exposure to core and emerging reliability topics presented by industry leaders. The tutorials are organized into 4 "tracks" this year _ Intro, Product, Circuit, and Device. For those who are new to the field of reliability, the Intro track offers introductory tutorials on topics of general and emerging interest. Product, Circuit, and Device tracks offer the experienced engineer an opportunity to hear new developments, exchange technical viewpoints, and broaden their technical skills in these reliability focus areas.
The topics for 2001 include core presentations in the areas of transistor, gate oxide, and Cu interconnect reliability. These areas are of continuing concern in the reliability community as the semiconductor industry steadily pushes for aggressive technology scaling with new materials. At the circuit level, presentations in the area of ESD protection and design reliability address the challenges of moving reliability "upstream" to the circuit simulation and design phase. This is critical in allowing reliable products to be introduced in a timely fashion. At the product level, new understanding and recent concern related to soft errors (SER) is addressed as well as two tutorials focused on product qualification. The first tutorial on qualification is from a semiconductor foundry perspective in the format of a panel discussion. The second tutorial focuses on qualification as an element of the entire product creation process considering increasing time-to-market pressures that exist today.
The 2001 tutorials also include an "Intro" track. One topic that is common to all areas of semiconductor reliability engineering is the statistical nature of reliability experimentation. This introductory tutorial addresses errors that can creep into reliability experiments and extrapolations, and steps that need to be taken to avoid them. Two other talks in the "Intro" track are on topics of emerging interest. The first addresses the thermal engineering aspect of semiconductor reliability. It is becoming increasingly important to understand how to control the temperature of IC's as power dissipation for high
performance products continues to climb. The second tutorial on an emerging topic is in the area of ferroelectric reliability. Ferroelectric materials and devices are gaining more widespread use and it is becoming important to understand the unique reliability challenges that are associated with them.
The Tutorials program is a great value for IRPS attendees. It is far more economical than bringing experts to your location. With the registration you will receive a copy of the Tutorials Notes which includes the abstracts and viewgraphs of all the tutorials (over 20 hours of reference material!). To facilitate meeting room planning, you are strongly encouraged to register early and indicate your intended attendance choices on the registration card.
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Topic 1. Errors Made When Performing Reliability Experiments: Discussion, Consequences and Applications—L. Tielemans, DESTIN N.V., Diepenbeek, Belgium and K. Croes, IMO, LUC, Diepenbeek, Belgium (8:00 a.m. - 11:30 a.m., Scotland)
One of the main purposes of performing reliability experiments is to obtain information on the lifetime of the tested component or system under normal operating conditions. Of course, when estimating such a lifetime at the very end of a testing period, the obtained estimate is subject to all types of error. The main idea of this tutorial is to present an overview of all the potential errors that can be made on the predicted lifetimes.
Topic 2. Silicon Amnesia: A Tutorial on Radiation Induced Soft Errors—R. Baumann, Texas Instruments (8:00 a.m. - 9:30 a.m., England)
With the advent of multi-megabyte embedded memories and technologies with stratospheric transistor counts doing billions of operations per second, all the while operating at voltages approaching threshold voltages, the once ephemeral soft error is rapidly coalescing into a very real concern for a large variety of customers. In this tutorial we will consider how radiation-induced charge generation, transport, and collection can induce soft error events in memory and in logic circuits. We will examine, in detail, the three different radiation mechanisms responsible for soft errors and how these radiation sources can be quantified. Finally, we will discuss the various methods used to determine the impact of soft errors on product performance and design and process methodologies which can greatly reduce the soft error rate.
Topic 3. Semiconductor Foundry Qualification Panel Discussion— Panel Members: R. Hijab, Cirrus Logic, Y.J. Chang, UMC, C.-K. Lau, Chartered, A. Preussger, Infineon, and J. Yue, TSMC (10:00 a.m. - 11:30 a.m., England)
Questions to be addressed:
• How do customers know that designs fabricated in semiconductor foundries are free from wearout issues?
• How do semiconductor foundries handle user defined reliability requirements?
• What changes to the qualification strategy and challenges does the semiconductor foundry business anticipate with regard to the introduction of new materials and processes (i.e. Cu / low-k)?
Topic 4. New Phenomena in the Device Reliability Physics of Advanced Submicron CMOS Technologies—G. La Rosa, S. Rauch, and F. Guarin, IBM Microelectronics, Hopewell Junction, NY(8:00 a.m. - 11:30 a.m., Ireland)
This tutorial will give an overview of some of the new reliability phenomena observed in MOSFET devices of advanced submicron CMOS technologies and their impact to reliability lifetime projections. Some focus will be given to Hot Carrier Reliability Phenomena such as e-e scattering, secondary impact ionization as well as parasitic drain series resistance effects in NMOSFET as well as hot hole damage in PMOSFET devices. In addition the role of Negative Bias Temperature Instabilites (NBTI) as technology limiter in the design of PMOSFET submicron devices will be discussed. The impact of these phenomena to DC and AC based circuit lifetime projections as well as methodologies will be given.
Topic 5. ESD Reliability Physics, Devices and Circuits—S.H. Voldman, IBM, Essex Junction, VT(8:00 a.m. - 11:30 a.m., Great Hall North)
With technology scaling, introduction of new technology types and growth of RF wireless applications, there continues to be a sustained need for understanding ESD phenomenon, providing new ESD solutions, innovations and inventions. In this tutorial, ESD protection of semiconductor devices in advanced CMOS, BiCMOS, Silicon on Insulator (SOI), Silicon on Sapphire (SOS), Gallium Arsenide, and Silicon Germanium (SiGe) technology as well as new ESD disciplines will be discussed. ESD reliability physics of known physical models of silicon devices and interconnects (e.g., Wunsch-Bell, and Dwyer) will first be reviewed and how they relate to ESD protection and ESD pulse models (e.g., HBM, MM, CDM, TLP and VF-TLP) will be discussed. CMOS MOSFET scaling and technology evolution, with the introduction of shallow trench isolation, cobalt salicide, copper interconnects, low K dielectrics and gate dielectric scaling will be reviewed in light of its implications, impacts, advantages and disadvantages to ESD protection. ESD devices, circuits and techniques will be discussed commonly used in memory, microprocessors, and logic. MOSFET-based (e.g., grounded gate, RC- and substrate-triggered) and diode-based ESD networks, as well as ESD Power Clamps, will be reviewed and compared. New SOI ESD physics, circuits and inventions (e.g. SOI lateral polysilicon diode, dynamic threshold body-coupled ESD) will be discussed. Our focus will then shift to BiCMOS, BiCMOS SiGe, RF-CMOS, RF-SOS and GaAs ESD. Power-to-failure, SOA, the Johnson limit, RF fT fMAX tradeoffs and ESD will be highlighted for Silicon Germanium technology. Additionally, ESD physics in non-silicon applications (e.g. semiconductor masks, and the MR, Giant MR and Tunneling MR devices for disk drive industry) will also be highlighted.
Topic 6. Aerosol Spray and the Cooling of Microelectronics—P.J. Boudreaux, Laboratory for Physical Sciences, College Park, MD and D.E. Tilton, Isothermal Systems Research, Inc., Clarkston, WA (1:30 p.m. - 3:00 p.m., Scotland)
Since the advent of VLSI microelectronics, there has been a steady demand for higher and higher performance with a concomitant heat load. This has placed an increasing burden on the thermal capabilities of microelectronic systems. New technological breakthroughs have greatly alleviated this thermal bottleneck and aerosol spray cooling is one of them. It has unique characteristics to add to the thermal design and control of microelectronics. A new thermal management paradigm is possible that greatly enhances the reliability while reducing the overall system size and weight. This liquid phase change technology allows the designer to minimize the maximum temperatures in a system while simultaneously eliminating most of the temperature gradients across components. Aerosol spray cooling is described along with some example applications, which illustrate the remarkable characteristics of this technology.
Topic 7. A Chip Designers Perspective on Reliability—D. Overhauser, Simplex, Sunnyvale, CA (1:30 p.m. - 3:00 p.m., Ireland)
As mainstream designs move to 0.18-micron processes and below, and increase both design size and power, more chip designers are making reliability analysis a standard part of their design flow. The quality of the analysis varies significantly between different design teams. More aggressive designs require much more extensive analysis of both the process and the design. This tutorial will provide an overview of the approaches to reliability analysis by various design teams for power grids and signal nets. Various methodologies, process analyses, design analyses, and analysis tools will be discussed.
Topic 8. Thin Gate Oxide Reliability: Degradation, Statistics and Breakdown Modes—J. Suñé, Universitat Autònoma de Barcelona, Bellaterra, Spain and E. Miranda, Universidad de Buenos Aires, Buenos Aires, Argentina (1:30 p.m. - 3:00 p.m., Great Hall North)
The dielectric breakdown of thin gate oxides in MOS devices is reviewed with particular emphasis in three relevant issues: oxide degradation, breakdown statistics, and breakdown modes. If one assumes that oxide breakdown is related to the generation of defects in the oxide bulk, the study of oxide degradation under electrical stress is essential. A critical analysis of the different physical models accounting for oxide degradation is briefly presented. The link between defect generation and breakdown has been established by means of simple statistical considerations. A brief overview of the breakdown statistics including the discussion of various models is included. Particular interest is given to a very simple physics-based analytical picture that shares the main features of the numerical percolation models. In thin oxides, at least two different breakdown modes have been identified, namely Soft Breakdown (SBD) and Hard Breakdown (HBD). Understanding the physics underlying these conduction modes is a major concern because SBD might be tolerated at least for some digital applications. We discuss how these breakdown modes show coincident time-to-breakdown statistics in spite of exhibiting huge differences in the post-breakdown current. The properties of both breakdown modes are explained in the common framework of a model based on quantum point contact conduction. The energy dissipation mechanisms that control the prevalence ratio of SBD and HBD events during the breakdown runaway will also be briefly discussed.
Topic 9. Ferroelectric Material and Device Reliability—T. D. Hadnagy, Ramtron International Inc., Colorado Springs, CO(3:30 p.m. - 5:00 p.m.,Scotland)
The last few years has seen the introduction of ferroelectrics based memories. The materials of choice have been PZT and SBT (Y1). There has been extensive research done in the integration of these materials into standard CMOS processing. This work has revealed many issues associated with the control of ferroelectrics properties. Included in these issues is the necessity of not degrading the ferroelectric device properties, the electroding system and maintaining the CMOS device performance. These issues have had a direct impact on the reliability of the final products produced with a particular process flow. Reviewed will be the current understanding about the issues associated with both of the main materials contenders. In particular, the materials properties will be reviewed as a function of processing conditions and deposition conditions. Materials attributes and how they tie into product reliability and ultimately system requirements will be reviewed. Details associated with the major failure modes of ferroelectric memories will be discussed as well as methods circumventing them. The impact of processing conditions as well as materials choices on reliability will be discussed. Process integration issues are currently at a high level of interest and a number of different
solutions are being pursued to address the issues of materials degradation. These include but are not limited to change of electrode structure, capacitor encapsulation methods, as well as process integration changes. The delivery of products to customers and the implementation of quality control mechanisms often reveal low percentage failure mechanisms that are either materials or process related. Finally the current status of product performance to industry standard reliability tests and future directions will be evaluated with an eye on trends and possible markets.
Topic 10. Microstructure, Processing and Reliability of Cu-Based Interconnect Structures—J. Sanchez, Jr., Advanced Micro Devices, Sunnyvale, CA (3:30 p.m. - 5:00 p.m., Great Hall North)
The implementation of Cu-based interconnect structures is the result of the development of novel processing schemes and the learning of new paradigms for structure-processing relationships, as well the application of relevant portions of the existing Al-based interconnect knowledge foundation. As an example, the challenging tight pitch metallization schemes for 130 nm generation technologies and beyond, require novel damascene patterning of Cu-filled trenches filled by bottom-up electroplating. The stringent Cu diffusion barrier and electroplating requirements dictate refractory metal and Cu "seed" layers, however experience learned during Al-based multilayer metallization development may be applied to barrier metal/Cu interconnect process development. In addition, basic materials' properties and processing effects will also determine the mechanisms controlling Cu interconnect reliability, although the degree to which individual mechanisms may vary since typical Cu microstructures and mechanical properties vary from typical Al-based structures. This tutorial will describe the key factors that control Cu interconnect reliability: interconnect microstructure and the dependence on processing schemes; mechanical stresses and the dependence on dielectric constraint and thermal processing; and diffusional mechanisms that determine stress evolution, voiding, delamination and interconnect failure.
Topic 11 Qualification for Reliability in Time-to-Market Driven Product Creation Processes—W. Gerling, Infineon Technologies AG, Muenchen, Germany and F.-W. Wulfert, Motorola SPS, Muenchen, Germany (1:30 p.m. - 5:00 p.m., England)
The penetration of semiconductor products into the variety of application segments together with their economic forces of cost and time-to-market enforce more efficient qualification concepts. This influences the organization of the qualification process in relation to the development / innovation process as well as the choice of qualification methodology. This tutorial will introduce a systematic procedure which makes best use of existing knowledge (existing qualification results) and focuses on the aspects which need to be qualified, and an application specific qualification methodology based on the physics of failure, which is adjustable to the requirements of different application segments. Visual examples will also be provided.