Tuesday, May 1, 8:00 a.m., Great Hall

• 1. PRODUCT RELIABILITY I
  (summary covers both sessions 1 and 4a)

Experimental techniques and monitoring strategies describing the product reliability of DRAM and NVM memories are explored. The compilation of papers recognizes a correlation between retention time, erratic bits and reliability lifetime. DRAM scaling of the transfer device and it's inherent retention time influence is described, along with a test structure and applied conditions to determine the defect tail distribution. A novel test structure is also used to determine signal degradation and reliability in FERAM. Erratic FLASH bits are correlated to threshold voltage shifts. Finally a time zero PMOSFET monitoring scheme is shown to avert standby power fails that develop during product stress.

Analysis methodology, models, technology scaling, and product monitoring techniques are investigated. Emphasis is placed upon the synergy between known signatures and reliability robustness. IDDQ testing is used to analyze oxide reliability through its stress current signature. Dynamic voltage stress is shown to improve SRAM early life failure rate, and also enables a reduction in Burn-In. Soft error rate susceptibility in micro-processors is investigated in conjunction with technology and power supply scaling, b, indicating an increase awareness of the product core contribution to the overall chip FIT rate. An analytical model for determining FLASH retention time is presented, and a model proposing a distribution of activation energies (e.g. hydrogen defect) is described.

Tuesday, May 1, 2:00 p.m., Parallel Session (Great Hall North)

• 2A PROCESS & RELIABILITY INTERACTIONS

The theme of this session is the interaction of processing with the reliability of silicon devices. Papers cover CMP-related life test fails, STI-process related fails and processing effects on non-volatile memory reliability. Furthermore, two papers deal with fast, statistics-based characterization and the conduction mechanism of anomalous bits in flash devices.

Tuesday, May 1, 2:00 p.m., Parallel Session (Scotland)

• 2B MEMS RELIABILITY CHARACTERIZATION

This session will reveal how broad and diverse the MEMS area really is. The first paper is a classic reliability study of a new MEMS actuator. The next two papers deal with the characterization of actuators (measuring resonance) using stroboscopic techniques, one is an interferometric technique and the other is a non-destructive "plucking" technique. The fourth paper addresses the materials properties of thin polysilicon films using a new microtensile tester.

Tuesday, May 1, 4:05 p.m., Parallel Session (Scotland)

• 2C PACKAGING AND ASSEMBLY

The session opens with the invited presentation of the Best Paper from ESREF 2000. This is followed by a study of improving the long term integrity of micro-packages for MEMS applications in the human body. Solder fatigue is a focus due to current issues including the lead-free solders initiative, fine-pitch flip chip assembly and high temperature applications such as automotive. A theory for better predicting solder fatigue performance, and an innovative description of the damage incurred during accelerated thermal fatigue testing of board-level assemblies are presented.

Tuesday, May 1, 6:00 p.m. — 9:00 p.m., POSTER SESSION & RECEPTION (England/Ireland)

Wednesday, May 2, 8:00 a.m., Parallel Session (Great Hall North)

• 3A OXIDE I

This session covers several important oxide reliability issues, and features 2 invited papers from renowned experts. The reliability physics of ultrathin SiO₂ at low voltages will be discussed, followed by an ESR study identifying the atomic scale defects causing SILC. An AFM study confirms the nanometer scale of breakdown. The effects of the inversion layer density during stress on post-breakdown I-V characteristics are analyzed, and a method for calculating the errors in reliability estimates is presented.

Wednesday, May 2, 10:30 a.m., Parallel Session (Great Hall North)

• 3B WLR FOR INTERCONNECTS

The role of highly accelerated, fast wafer-level reliability (WLR) testing for evaluating interconnect reliability remains controversial. The first paper in this session compares various WLR methodologies. The next two papers evaluate the effectiveness of WLR tests to identify backend process variations that impact interconnect reliability. The last two papers include a comparison of WLR tests with conventional, long-term package tests.

Wednesday, May 2, 8:00 a.m., Parallel Session (Scotland)

• 3C OPTOELECTRONICS AND COMPOUND SEMICONDUCTOR

This session covers the reliability study and physics of optoelectronics and compound semiconductor devices. Three papers on the subjects of optoelectronics interconnect, InP heterojunction bipolar transistor (HBT), and GaN high electron mobility transistor (HEMT) have been selected for oral presentations. These papers provide useful and state of the art data concerning the degradation characteristics and reliability test data for the devices under study.

Wednesday, May 2, 10:30 a.m., Parallel Session (Scotland)

• 3D ESD/LATCHUP

In this session (6) papers will be presented. The topics covered investigate characterization and modeling of the parasitic lateral NPN bipolar for use as an ESD protection device, the interaction between hot electron and ESD, and the design of new protection structures for smart power technologies.

Wednesday, May 2, 12:10 p.m., AWARDS LUNCHEON (England/Ireland)

Wednesday, May 2, 2:00 p.m., (Great Hall North)

• 4A PRODUCT RELIABILITY II
  (summary covers both sessions 1 and 4a)

Experimental techniques and monitoring strategies describing the product reliability of DRAM and NVM memories are explored. The compilation of papers recognizes a correlation between retention time, erratic bits and reliability lifetime. DRAM scaling of the transfer device and it's inherent retention time influence is described, along with a test structure and applied conditions to determine the defect tail distribution. A novel test structure is also used to determine signal degradation and reliability in FERAM. Erratic FLASH bits are correlated to threshold voltage shifts. Finally a time zero PMOSFET monitoring scheme is shown to avert standby power fails that develop during product stress.

Analysis methodology, models, technology scaling, and product monitoring techniques are investigated. Emphasis is placed upon the synergy between known signatures and reliability robustness. IDDQ testing is used to analyze oxide reliability through its stress current signature. Dynamic voltage stress is shown to improve SRAM early life failure rate, and also enables a reduction in Burn-In. Soft error rate susceptibility in micro-processors is investigated in conjunction with technology and power supply scaling, b, indicating an increase awareness of the product core contribution to the overall chip FIT rate. An analytical model for determining FLASH retention time is presented, and a model proposing a distribution of activation energies (e.g. hydrogen defect) is described.

Wednesday, May 2, 3:40 p.m., Parallel Session (Great Hall North)

• 4B FAILURE ANALYSIS

The five papers in this session address various topics in failure analysis. The first paper describes how data is recovered from the Swissair 111 crash. The second paper describes a new technique for localizing electrical defects. The last three papers cover failure mechanisms related to various process parameters.

Wednesday, May 2, 2:00 p.m., (Scotland)

• 4C PROCESS INDUCED DAMAGE

In this session three papers are presented that are concerned with the effect of damage caused during wafer fabrication on device reliability. The first paper in this session relates trench geometry and silicon damage to UMOSFET reliability. The next paper shows a direct correlation between performance degradation on a FPGA product chip and the damage caused by a plasma ashing step. The final paper demonstrates an annealing process that carefully balances damage caused by the plasma with the benefits obtained from active hydrogen radicals produced by the plasma.

Wednesday, May 2, 3:40 p.m., (Scotland)

• 4D INTERCONNECT RELIABILITY

This session on interconnect reliability includes an eclectic group of topics: the effect of metal reservoirs on electromigration lifetime, stressmigration and the effect of stress voiding on electromigration, the trade-off between post-CMP defects and improved electromigration lifetime from annealing of copper interconnects, and characterization of TDDB in Cu/low-k interconnect systems.

Wednesday, May 2, 7:30 p.m. — 9:30 p.m., WORKSHOPS

Thursday, May 3, 8:00 a.m., (Great Hall North)

• 5. OXIDE II

This session continues the discussion of critical oxide reliability issues. A method for determining the breakdown position in transistors and the relation to breakdown mode is presented. An analytical model encompassing soft breakdown, hard breakdown, and SILC is proposed. An experiment supporting the anode hole injection model predictions of TDDB voltage acceleration factor scalability is shown, followed by 2 papers on soft breakdown detection algorithms.

Thursday, May 3, 10:30 a.m., (Great Hall North)

• "Is Burn-in elimation Possible?"—PANEL DISCUSSION

Thursday, May 3, 2:00 p.m., (Great Hall North)

• 6. HOT CARRIERS

Hot Carrier phenomena play a critical role in the reliability of advanced CMOS technologies. This year session has three papers reporting new insights on the role of EE scattering, interface states generation as well as hole/electron trapping to the HC Physics and behavior. In addition the HC reliability of Si₃N₄ and STI narrow MOSFETs are covered.